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drm/amd/display: Move DPM clk read to clk_mgr_construct in DCN42
[Why&How] The DPM clocks on DCN42 are currently read on every dm_resume, which can cause in gpu memory freeing while the device is still in suspend. Move the DPM clock read functionality to clk_mgr_construct() so it completes once on driver enablement. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ivan Lipski
Alex Deucher
parent
24ccc041f0
commit
058cb97b73
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@ -569,7 +569,6 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int);
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struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 };
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DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
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(void)dc_logger;
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@ -591,127 +590,6 @@ void dcn42_init_clocks(struct clk_mgr *clk_mgr_base)
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/*dtbclk enabled based on*/
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clk_mgr_base->clks.dtbclk_en = true;
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}
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if (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels != 0) {
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/*skip to get clock table and notify pmfw watermark range again*/
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DC_LOG_SMU("skip to get dpm_clks from pmfw from resume and acr\n");
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return;
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}
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smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem(
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clk_mgr_base->ctx,
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DC_MEM_ALLOC_TYPE_GART,
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sizeof(DpmClocks_t_dcn42),
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&smu_dpm_clks.mc_address.quad_part);
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ASSERT(smu_dpm_clks.dpm_clks);
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if (clk_mgr_base->ctx->dc->debug.pstate_enabled && clk_mgr_int->smu_present && smu_dpm_clks.mc_address.quad_part != 0) {
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int i;
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DpmClocks_t_dcn42 *dpm_clks = smu_dpm_clks.dpm_clks;
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dcn42_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks);
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DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
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"NumDispClkLevelsEnabled: %d\n"
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"NumSocClkLevelsEnabled: %d\n"
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"VcnClkLevelsEnabled: %d\n"
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"FClkLevelsEnabled: %d\n"
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"NumMemPstatesEnabled: %d\n"
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"MinGfxClk: %d\n"
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"MaxGfxClk: %d\n",
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dpm_clks->NumDcfClkLevelsEnabled,
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dpm_clks->NumDispClkLevelsEnabled,
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dpm_clks->NumSocClkLevelsEnabled,
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dpm_clks->VcnClkLevelsEnabled,
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dpm_clks->NumFclkLevelsEnabled,
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dpm_clks->NumMemPstatesEnabled,
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dpm_clks->MinGfxClk,
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dpm_clks->MaxGfxClk);
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for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->DcfClocks[%d] = %d\n",
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i,
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dpm_clks->DcfClocks[i]);
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}
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for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->DispClocks[%d] = %d\n",
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i, dpm_clks->DispClocks[i]);
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}
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for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->SocClocks[%d] = %d\n",
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i, dpm_clks->SocClocks[i]);
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}
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for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->FclkClocks_Freq[%d] = %d\n",
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i, dpm_clks->FclkClocks_Freq[i]);
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DC_LOG_SMU("dpm_clks->FclkClocks_Voltage[%d] = %d\n",
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i, dpm_clks->FclkClocks_Voltage[i]);
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}
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for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
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DC_LOG_SMU("dpm_clks->SocVoltage[%d] = %d\n",
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i, dpm_clks->SocVoltage[i]);
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for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks.MemPstateTable[%d].UClk = %d\n"
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"dpm_clks->MemPstateTable[%d].MemClk= %d\n"
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"dpm_clks->MemPstateTable[%d].Voltage = %d\n",
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i, dpm_clks->MemPstateTable[i].UClk,
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i, dpm_clks->MemPstateTable[i].MemClk,
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i, dpm_clks->MemPstateTable[i].Voltage);
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}
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if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) {
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/* DCFCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
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dpm_clks->DcfClocks,
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dpm_clks->NumDcfClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = dpm_clks->NumDcfClkLevelsEnabled;
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/* SOCCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
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dpm_clks->SocClocks,
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dpm_clks->NumSocClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels = dpm_clks->NumSocClkLevelsEnabled;
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/* DISPCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
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dpm_clks->DispClocks,
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dpm_clks->NumDispClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = dpm_clks->NumDispClkLevelsEnabled;
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/* DPPCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
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dpm_clks->DppClocks,
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dpm_clks->NumDispClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = dpm_clks->NumDispClkLevelsEnabled;
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/* FCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
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dpm_clks->FclkClocks_Freq,
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NUM_FCLK_DPM_LEVELS);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels = dpm_clks->NumFclkLevelsEnabled;
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clk_mgr_base->bw_params->clk_table.num_entries = dpm_clks->NumFclkLevelsEnabled;
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/* Memory Pstate table is in reverse order*/
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ASSERT(dpm_clks->NumMemPstatesEnabled <= NUM_MEM_PSTATE_LEVELS);
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if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS)
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dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS;
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for (i = 0; i < dpm_clks->NumMemPstatesEnabled; i++) {
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clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].UClk;
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clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio) ;
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}
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled;
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/* DTBCLK*/
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clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000;
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1;
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/* Refresh bounding box */
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clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
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clk_mgr_base->ctx->dc, clk_mgr_base->bw_params);
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}
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}
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if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
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dm_helpers_free_gpu_mem(clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART,
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smu_dpm_clks.dpm_clks);
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}
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static struct clk_bw_params dcn42_bw_params = {
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@ -1071,6 +949,127 @@ bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base)
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return clk_mgr->smu_present;
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}
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static void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int)
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{
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struct clk_mgr *clk_mgr_base = &clk_mgr_int->base;
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struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 };
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DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
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(void)dc_logger;
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smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem(
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clk_mgr_base->ctx,
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DC_MEM_ALLOC_TYPE_GART,
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sizeof(DpmClocks_t_dcn42),
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&smu_dpm_clks.mc_address.quad_part);
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ASSERT(smu_dpm_clks.dpm_clks);
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if (clk_mgr_base->ctx->dc->debug.pstate_enabled && smu_dpm_clks.mc_address.quad_part != 0) {
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int i;
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DpmClocks_t_dcn42 *dpm_clks = smu_dpm_clks.dpm_clks;
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dcn42_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks);
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DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
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"NumDispClkLevelsEnabled: %d\n"
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"NumSocClkLevelsEnabled: %d\n"
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"VcnClkLevelsEnabled: %d\n"
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"FClkLevelsEnabled: %d\n"
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"NumMemPstatesEnabled: %d\n"
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"MinGfxClk: %d\n"
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"MaxGfxClk: %d\n",
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dpm_clks->NumDcfClkLevelsEnabled,
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dpm_clks->NumDispClkLevelsEnabled,
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dpm_clks->NumSocClkLevelsEnabled,
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dpm_clks->VcnClkLevelsEnabled,
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dpm_clks->NumFclkLevelsEnabled,
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dpm_clks->NumMemPstatesEnabled,
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dpm_clks->MinGfxClk,
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dpm_clks->MaxGfxClk);
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for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->DcfClocks[%d] = %d\n",
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i,
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dpm_clks->DcfClocks[i]);
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}
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for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->DispClocks[%d] = %d\n",
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i, dpm_clks->DispClocks[i]);
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}
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for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->SocClocks[%d] = %d\n",
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i, dpm_clks->SocClocks[i]);
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}
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for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->FclkClocks_Freq[%d] = %d\n",
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i, dpm_clks->FclkClocks_Freq[i]);
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DC_LOG_SMU("dpm_clks->FclkClocks_Voltage[%d] = %d\n",
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i, dpm_clks->FclkClocks_Voltage[i]);
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}
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for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
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DC_LOG_SMU("dpm_clks->SocVoltage[%d] = %d\n",
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i, dpm_clks->SocVoltage[i]);
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for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks.MemPstateTable[%d].UClk = %d\n"
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"dpm_clks->MemPstateTable[%d].MemClk= %d\n"
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"dpm_clks->MemPstateTable[%d].Voltage = %d\n",
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i, dpm_clks->MemPstateTable[i].UClk,
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i, dpm_clks->MemPstateTable[i].MemClk,
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i, dpm_clks->MemPstateTable[i].Voltage);
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}
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if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) {
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/* DCFCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
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dpm_clks->DcfClocks,
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dpm_clks->NumDcfClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = dpm_clks->NumDcfClkLevelsEnabled;
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/* SOCCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
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dpm_clks->SocClocks,
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dpm_clks->NumSocClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels = dpm_clks->NumSocClkLevelsEnabled;
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/* DISPCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
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dpm_clks->DispClocks,
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dpm_clks->NumDispClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = dpm_clks->NumDispClkLevelsEnabled;
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/* DPPCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
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dpm_clks->DppClocks,
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dpm_clks->NumDispClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = dpm_clks->NumDispClkLevelsEnabled;
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/* FCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
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dpm_clks->FclkClocks_Freq,
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NUM_FCLK_DPM_LEVELS);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels = dpm_clks->NumFclkLevelsEnabled;
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clk_mgr_base->bw_params->clk_table.num_entries = dpm_clks->NumFclkLevelsEnabled;
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/* Memory Pstate table is in reverse order*/
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ASSERT(dpm_clks->NumMemPstatesEnabled <= NUM_MEM_PSTATE_LEVELS);
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if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS)
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dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS;
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for (i = 0; i < dpm_clks->NumMemPstatesEnabled; i++) {
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clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].UClk;
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clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio) ;
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}
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled;
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/* DTBCLK*/
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clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000;
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1;
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}
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}
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if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
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dm_helpers_free_gpu_mem(clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART,
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smu_dpm_clks.dpm_clks);
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}
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static struct clk_mgr_funcs dcn42_funcs = {
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.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
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.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
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@ -1139,6 +1138,11 @@ void dcn42_clk_mgr_construct(
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dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1;
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clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);
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clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base);
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clk_mgr->base.base.bw_params = &dcn42_bw_params;
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if (clk_mgr->base.smu_present)
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dcn42_get_smu_clocks(&clk_mgr->base);
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}
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/* in case we don't get a value from the BIOS, use default */
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if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
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@ -1151,8 +1155,6 @@ void dcn42_clk_mgr_construct(
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/*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
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dcn42_read_ss_info_from_lut(&clk_mgr->base);
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clk_mgr->base.base.bw_params = &dcn42_bw_params;
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}
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void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
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