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octeontx2-pf: Fix aura BPID assignment when CONFIG_DCB is enabled

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Previously, BPID assignment under CONFIG_DCB assumed
`queue_to_pfc_map` was always initialized. For SDP VFs this leads to
invalid memory access as it was not initialized.

This patch adds a NULL check for `queue_to_pfc_map` before
dereferencing it. Also, simplifies the logic by always assigning a
default BPID first, then conditionally overriding it if CONFIG_DCB is
enabled and the map exists.

Fixes: 184fb40f73 ("octeontx2-pf: Avoid adding dcbnl_ops for LBK and SDP vf")
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Subrat Pandey <subratp@marvell.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260922102149.2078168-2-subratp@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Geetha sowjanya 2026-09-22 15:51:48 +05:30 committed by Jakub Kicinski
parent 382cf97689
commit 0569945639
3 changed files with 16 additions and 20 deletions
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11
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
View File

@ -242,15 +242,6 @@ int cn20k_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
#define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */
static u8 cn20k_aura_bpid_idx(struct otx2_nic *pfvf, int aura_id)
{
#ifdef CONFIG_DCB
return pfvf->queue_to_pfc_map[aura_id];
#else
return 0;
#endif
}
static int cn20k_tc_get_entry_index(struct otx2_flow_config *flow_cfg,
struct otx2_tc_flow *node)
{
@ -580,7 +571,7 @@ static int cn20k_aura_aq_init(struct otx2_nic *pfvf, int aura_id,
if (pfvf->nix_blkaddr == BLKADDR_NIX1)
aq->aura.bp_ena = 1;
bpid_idx = cn20k_aura_bpid_idx(pfvf, aura_id);
bpid_idx = otx2_get_bpid_idx(pfvf, aura_id);
aq->aura.bpid = pfvf->bpid[bpid_idx];
/* Set backpressure level for RQ's Aura */

16
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
View File

@ -1055,6 +1055,7 @@ int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
struct nix_aq_enq_req *aq;
struct otx2_cq_queue *cq;
struct otx2_pool *pool;
u8 bpid_idx;
cq = &qset->cq[qidx];
cq->cq_idx = qidx;
@ -1132,11 +1133,8 @@ int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
if (!is_otx2_lbkvf(pfvf->pdev)) {
/* Enable receive CQ backpressure */
aq->cq.bp_ena = 1;
#ifdef CONFIG_DCB
aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]];
#else
aq->cq.bpid = pfvf->bpid[0];
#endif
bpid_idx = otx2_get_bpid_idx(pfvf, qidx);
aq->cq.bpid = pfvf->bpid[bpid_idx];
/* Set backpressure level is same as cq pass level */
aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
@ -1378,6 +1376,7 @@ int otx2_aura_aq_init(struct otx2_nic *pfvf, int aura_id,
{
struct npa_aq_enq_req *aq;
struct otx2_pool *pool;
u8 bpid_idx;
int err;
pool = &pfvf->qset.pool[pool_id];
@ -1433,11 +1432,8 @@ int otx2_aura_aq_init(struct otx2_nic *pfvf, int aura_id,
*/
if (pfvf->nix_blkaddr == BLKADDR_NIX1)
aq->aura.bp_ena = 1;
#ifdef CONFIG_DCB
aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]];
#else
aq->aura.nix0_bpid = pfvf->bpid[0];
#endif
bpid_idx = otx2_get_bpid_idx(pfvf, aura_id);
aq->aura.nix0_bpid = pfvf->bpid[bpid_idx];
/* Set backpressure level for RQ's Aura */
aq->aura.bp = RQ_BP_LVL_AURA;

9
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
View File

@ -1029,6 +1029,15 @@ static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf)
return pfvf->flow_cfg->nr_flows;
}
static inline u8 otx2_get_bpid_idx(struct otx2_nic *pfvf, int qidx)
{
#ifdef CONFIG_DCB
if (pfvf->queue_to_pfc_map)
return pfvf->queue_to_pfc_map[qidx];
#endif
return 0;
}
/* MSI-X APIs */
void otx2_free_cints(struct otx2_nic *pfvf, int n);
void otx2_set_cints_affinity(struct otx2_nic *pfvf);