From 0549cdb08a846babf44ea97a03d866dbcfc17873 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Thu, 7 May 2026 14:53:28 +0800 Subject: [PATCH] arm64: dts: imx8mp-evk: Disable PCIe bus in the default dts Disable the PCIe bus in the default device tree to avoid shared regulator conflicts between SDIO and PCIe buses. The non-deterministic probe order between these two buses can break the PCIe initialization sequence, causing PCIe devices to fail detection intermittently. On i.MX8MP EVK board, the M.2 connector is physically wired to both USDHC1 and PCIe0, however the out-of-box module is SDIO IW612 WiFi, so enable the SDIO WiFi in the default imx8mp-evk.dts. Add 'm2_usdhc' label to USDHC1 to support device tree overlay for PCIe modules. Users who need PCIe can use imx8mp-evk-pcie.dtb (added in a follow-up patch) which applies an overlay to enable PCIe and disable USDHC1. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index d0a2bd975a18..2feb5b18645c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -774,7 +774,7 @@ &pcie0 { vpcie-supply = <®_pcie0>; vpcie3v3aux-supply = <®_pcie0>; supports-clkreq; - status = "okay"; + status = "disabled"; }; &pcie0_ep { @@ -870,7 +870,7 @@ &uart3 { status = "okay"; }; -&usdhc1 { +m2_usdhc: &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>;