From 05112f1fc363d19105ecfce3eec637e63b50cde8 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Tue, 3 Mar 2026 20:07:58 -0500 Subject: [PATCH] drm/amd/display: Move DPM clk read to clk_mgr_construct in DCN42 [Why&How] The DPM clocks on DCN42 are currently read on every dm_resume, which can cause in gpu memory freeing while the device is still in suspend. Move the DPM clock read functionality to clk_mgr_construct() so it completes once on driver enablement. Reviewed-by: Charlene Liu Signed-off-by: Ivan Lipski Signed-off-by: Dmytro Laktyushkin Signed-off-by: Chuanyu Tseng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 24834f89711d..5671fe481d15 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -1146,6 +1146,11 @@ void dcn42_clk_mgr_construct( dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; + + if (clk_mgr->base.smu_present) + dcn42_get_smu_clocks(&clk_mgr->base); } /* in case we don't get a value from the BIOS, use default */ if (clk_mgr->base.base.dentist_vco_freq_khz == 0)