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arm64: dts: rockchip: assign pipe clock to rk356x PCIe lanes
These clocks are used by PCIe lanes, but we're missing from the definition. Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://patch.msgid.link/20260304-rk3568-bri-r2-pro-fix-pcie-v4-1-37abd7ba29d0@ixit.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
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bus-range = <0x10 0x1f>;
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clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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<&cru CLK_PCIE30X1_AUX_NDFT>;
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<&cru CLK_PCIE30X1_AUX_NDFT>,
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<&cru CLK_PCIE30X1_PIPE_DFT>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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"aclk_dbi", "pclk", "aux",
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"pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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<&cru CLK_PCIE30X2_AUX_NDFT>;
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<&cru CLK_PCIE30X2_AUX_NDFT>,
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<&cru CLK_PCIE30X2_PIPE_DFT>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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"aclk_dbi", "pclk", "aux",
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"pipe";
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device_type = "pci";
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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@ -1020,9 +1020,11 @@ pcie2x1: pcie@fe260000 {
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bus-range = <0x0 0xf>;
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clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
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<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
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<&cru CLK_PCIE20_AUX_NDFT>;
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<&cru CLK_PCIE20_AUX_NDFT>,
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<&cru CLK_PCIE20_PIPE_DFT>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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"aclk_dbi", "pclk", "aux",
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"pipe";
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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