arm64: dts: rockchip: assign pipe clock to rk356x PCIe lanes

These clocks are used by PCIe lanes, but we're missing from the
definition.

Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/20260304-rk3568-bri-r2-pro-fix-pcie-v4-1-37abd7ba29d0@ixit.cz
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
David Heidelberg 2026-03-04 12:05:27 +01:00 committed by Heiko Stuebner
parent 792c42da47
commit 04eeaf39f8
2 changed files with 12 additions and 6 deletions

View File

@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
<&cru CLK_PCIE30X1_AUX_NDFT>,
<&cru CLK_PCIE30X1_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk", "aux",
"pipe";
device_type = "pci";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
<&cru CLK_PCIE30X2_AUX_NDFT>,
<&cru CLK_PCIE30X2_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk", "aux",
"pipe";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

View File

@ -1020,9 +1020,11 @@ pcie2x1: pcie@fe260000 {
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
<&cru CLK_PCIE20_AUX_NDFT>;
<&cru CLK_PCIE20_AUX_NDFT>,
<&cru CLK_PCIE20_PIPE_DFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk", "aux",
"pipe";
device_type = "pci";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;