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usb: dwc3: core: Disable USB2 retry for DWC_usb31 1.80a and prior

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STAR 9001346572 addresses a USB 2.0 endpoint blocking issue in host mode
for controller versions DWC_usb31 1.70a and 1.80a. This issue affects
devices on both high-speed and full-speed bus instances. When all
endpoint caches are filled and a single active endpoint receives
continuous NAK responses, data transfers to other endpoints may get
blocked.

To resolve this, for controller versions DWC_usb31 1.70a and 1.80a, the
GUCTL3 bit[16] (USB2.0 Internal Retry Disable) is set to 1. This bit
disables the USB2.0 internal retry feature and ensures proper eviction
handling in the host controller endpoind cache. The GUCTL3[16] register
function is available only from DWC_usb31 version 1.70a.

Signed-off-by: Faisal Hassan <quic_faisalh@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20241129173422.20063-1-quic_faisalh@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Faisal Hassan 2024-11-29 23:04:22 +05:30 committed by Greg Kroah-Hartman
parent a787bffff5
commit 04d5b4c23f
2 changed files with 21 additions and 0 deletions
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20
drivers/usb/dwc3/core.c
View File

@ -1479,6 +1479,26 @@ static int dwc3_core_init(struct dwc3 *dwc)
}
}
/*
* STAR 9001346572: This issue affects DWC_usb31 versions 1.80a and
* prior. When an active endpoint not currently cached in the host
* controller is chosen to be cached to the same index as an endpoint
* receiving NAKs, the endpoint receiving NAKs enters continuous
* retry mode. This prevents it from being evicted from the host
* controller cache, blocking the new endpoint from being cached and
* serviced.
*
* To resolve this, for controller versions 1.70a and 1.80a, set the
* GUCTL3 bit[16] (USB2.0 Internal Retry Disable) to 1. This bit
* disables the USB2.0 internal retry feature. The GUCTL3[16] register
* function is available only from version 1.70a.
*/
if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE;
dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
}
return 0;
err_power_off_phy:

1
drivers/usb/dwc3/core.h
View File

@ -425,6 +425,7 @@
/* Global User Control Register 3 */
#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
#define DWC3_GUCTL3_USB20_RETRY_DISABLE BIT(16)
/* Device Configuration Register */
#define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */