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dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml

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With the conversion of rockchip,rk3399-cru.txt a table with external clocks
was copied. Make it a bit cleaner by aligning the columns. Also fix
a description. Phrases start with a capital.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220329150742.22093-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Johan Jonker 2022-03-29 17:07:37 +02:00 committed by Heiko Stuebner
parent 3123109284
commit 04d3e42714
1 changed files with 7 additions and 7 deletions
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14
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
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@ -22,11 +22,11 @@ description: |
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "clkin_gmac" - external GMAC clock - optional,
- "clkin_i2s" - external I2S clock - optional,
- "pclkin_cif" - external ISP clock - optional,
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "clkin_gmac" - external GMAC clock - optional,
- "clkin_i2s" - external I2S clock - optional,
- "pclkin_cif" - external ISP clock - optional,
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
@ -62,8 +62,8 @@ properties:
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description: >
phandle to the syscon managing the "general register files". It is used
description:
Phandle to the syscon managing the "general register files". It is used
for GRF muxes, if missing any muxes present in the GRF will not be
available.