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drm/amdgpu/pm: add documentation for pp_od_clock_voltage for APUs

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APUs only support adjusting the SCLK domain.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2021-04-30 12:21:46 -04:00
parent cfd053be1f
commit 0487bbb444
1 changed files with 8 additions and 0 deletions
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8
drivers/gpu/drm/amd/pm/amdgpu_pm.c
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@ -735,6 +735,14 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
* - a list of valid ranges for sclk, mclk, and voltage curve points
* labeled OD_RANGE
*
* < For APUs >
*
* Reading the file will display:
*
* - minimum and maximum engine clock labeled OD_SCLK
*
* - a list of valid ranges for sclk labeled OD_RANGE
*
* To manually adjust these settings:
*
* - First select manual using power_dpm_force_performance_level