github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-01 11:03:43 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Merge branch 'net-stmmac-eic7700-fix-delay-calculation-and-initialization-ordering'

Browse Source 
Zhi Li says:

====================
net: stmmac: eic7700: fix delay calculation and initialization ordering

From: Zhi Li <lizhi2@eswincomputing.com>
====================

Link: https://patch.msgid.link/20260518021919.404-1-lizhi2@eswincomputing.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni 2026-05-21 11:58:18 +02:00
commit 0377bd2722
2 changed files with 102 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
View File

@ -73,6 +73,15 @@ properties:
HSP CSR is to control and get status of different high-speed peripherals
(such as Ethernet, USB, SATA, etc.) via register, which can tune
board-level's parameters of PHY, etc.
Additional background information about the High-Speed Subsystem
and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
of the EIC7700X SoC Technical Reference Manual, Part 4
(EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
publicly available at
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
This reference is provided for background information only.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
@ -82,6 +91,8 @@ properties:
- description: Offset of AXI clock controller Low-Power request
register
- description: Offset of register controlling TX/RX clock delay
- description: Optional offset of register controlling TXD delay
- description: Optional offset of register controlling RXD delay
required:
- compatible
@ -116,7 +127,7 @@ examples:
reset-names = "stmmaceth";
rx-internal-delay-ps = <200>;
tx-internal-delay-ps = <200>;
eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
snps,axi-config = <&stmmac_axi_setup>;
snps,aal;
snps,fixed-burst;

128
drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
View File

@ -28,13 +28,16 @@
/*
* TX/RX Clock Delay Bit Masks:
* - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit)
* - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit)
* - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.02ns per bit)
* - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.02ns per bit)
*/
#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8)
#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24)
#define EIC7700_MAX_DELAY_UNIT 0x7F
#define EIC7700_MAX_DELAY_STEPS 0x7F
#define EIC7700_DELAY_STEP_PS 20
#define EIC7700_MAX_DELAY_PS \
(EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS)
static const char * const eic7700_clk_names[] = {
"tx", "axi", "cfg",
@ -42,6 +45,15 @@ static const char * const eic7700_clk_names[] = {
struct eic7700_qos_priv {
struct plat_stmmacenet_data *plat_dat;
struct regmap *eic7700_hsp_regmap;
u32 eth_axi_lp_ctrl_offset;
u32 eth_phy_ctrl_offset;
u32 eth_clk_offset;
u32 eth_txd_offset;
u32 eth_rxd_offset;
u32 eth_clk_dly_param;
bool has_txd_offset;
bool has_rxd_offset;
};
static int eic7700_clks_config(void *priv, bool enabled)
@ -61,8 +73,34 @@ static int eic7700_clks_config(void *priv, bool enabled)
static int eic7700_dwmac_init(struct device *dev, void *priv)
{
struct eic7700_qos_priv *dwc = priv;
int ret;
return eic7700_clks_config(dwc, true);
ret = eic7700_clks_config(dwc, true);
if (ret)
return ret;
ret = regmap_set_bits(dwc->eic7700_hsp_regmap,
dwc->eth_phy_ctrl_offset,
EIC7700_ETH_TX_CLK_SEL |
EIC7700_ETH_PHY_INTF_SELI);
if (ret) {
eic7700_clks_config(dwc, false);
return ret;
}
regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset,
EIC7700_ETH_CSYSREQ_VAL);
if (dwc->has_txd_offset)
regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0);
if (dwc->has_rxd_offset)
regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0);
regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset,
dwc->eth_clk_dly_param);
return 0;
}
static void eic7700_dwmac_exit(struct device *dev, void *priv)
@ -93,13 +131,7 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
struct plat_stmmacenet_data *plat_dat;
struct stmmac_resources stmmac_res;
struct eic7700_qos_priv *dwc_priv;
struct regmap *eic7700_hsp_regmap;
u32 eth_axi_lp_ctrl_offset;
u32 eth_phy_ctrl_offset;
u32 eth_phy_ctrl_regset;
u32 eth_rxd_dly_offset;
u32 eth_dly_param = 0;
u32 delay_ps;
u32 delay_ps, val;
int i, ret;
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
@ -119,10 +151,20 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
/* Read rx-internal-delay-ps and update rx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"rx-internal-delay-ps", &delay_ps)) {
u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
if (delay_ps % EIC7700_DELAY_STEP_PS)
return dev_err_probe(&pdev->dev, -EINVAL,
"rx delay must be multiple of %dps\n",
EIC7700_DELAY_STEP_PS);
eth_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
eth_dly_param |= FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
if (delay_ps > EIC7700_MAX_DELAY_PS)
return dev_err_probe(&pdev->dev, -EINVAL,
"rx delay out of range\n");
val = delay_ps / EIC7700_DELAY_STEP_PS;
dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
dwc_priv->eth_clk_dly_param |=
FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
} else {
return dev_err_probe(&pdev->dev, -EINVAL,
"missing required property rx-internal-delay-ps\n");
@ -131,55 +173,65 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
/* Read tx-internal-delay-ps and update tx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"tx-internal-delay-ps", &delay_ps)) {
u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
if (delay_ps % EIC7700_DELAY_STEP_PS)
return dev_err_probe(&pdev->dev, -EINVAL,
"tx delay must be multiple of %dps\n",
EIC7700_DELAY_STEP_PS);
eth_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
eth_dly_param |= FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
if (delay_ps > EIC7700_MAX_DELAY_PS)
return dev_err_probe(&pdev->dev, -EINVAL,
"tx delay out of range\n");
val = delay_ps / EIC7700_DELAY_STEP_PS;
dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
dwc_priv->eth_clk_dly_param |=
FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
} else {
return dev_err_probe(&pdev->dev, -EINVAL,
"missing required property tx-internal-delay-ps\n");
}
eic7700_hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"eswin,hsp-sp-csr");
if (IS_ERR(eic7700_hsp_regmap))
dwc_priv->eic7700_hsp_regmap =
syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"eswin,hsp-sp-csr");
if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
return dev_err_probe(&pdev->dev,
PTR_ERR(eic7700_hsp_regmap),
PTR_ERR(dwc_priv->eic7700_hsp_regmap),
"Failed to get hsp-sp-csr regmap\n");
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
1, &eth_phy_ctrl_offset);
1, &dwc_priv->eth_phy_ctrl_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_phy_ctrl_offset\n");
regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset,
&eth_phy_ctrl_regset);
eth_phy_ctrl_regset |=
(EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI);
regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset,
eth_phy_ctrl_regset);
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
2, &eth_axi_lp_ctrl_offset);
2, &dwc_priv->eth_axi_lp_ctrl_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_axi_lp_ctrl_offset\n");
regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset,
EIC7700_ETH_CSYSREQ_VAL);
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
3, &dwc_priv->eth_clk_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_clk_offset\n");
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
3, &eth_rxd_dly_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_rxd_dly_offset\n");
4, &dwc_priv->eth_txd_offset);
if (!ret)
dwc_priv->has_txd_offset = true;
regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset,
eth_dly_param);
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
5, &dwc_priv->eth_rxd_offset);
if (!ret)
dwc_priv->has_rxd_offset = true;
plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
plat_dat->clks = devm_kcalloc(&pdev->dev,