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arm64: tegra: Use correct format for clocks property

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phandle and clock specifier pairs should be enclosed in angular
brackets.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2023-08-17 16:14:05 +02:00
parent 4bf7fa33d1
commit 036f15c248
1 changed files with 16 additions and 16 deletions
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32
arch/arm64/boot/dts/nvidia/tegra234.dtsi
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@ -705,8 +705,8 @@ gen1_i2c: i2c@3160000 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C1
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C1>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@ -724,8 +724,8 @@ cam_i2c: i2c@3180000 {
#size-cells = <0>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C3
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C3>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@ -743,8 +743,8 @@ dp_aux_ch1_i2c: i2c@3190000 {
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C4
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C4>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@ -762,8 +762,8 @@ dp_aux_ch0_i2c: i2c@31b0000 {
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C6
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C6>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@ -781,8 +781,8 @@ dp_aux_ch2_i2c: i2c@31c0000 {
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C7
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C7>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@ -807,8 +807,8 @@ dp_aux_ch3_i2c: i2c@31e0000 {
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C9
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C9>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@ -1751,8 +1751,8 @@ gen2_i2c: i2c@c240000 {
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C2
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C2>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
@ -1770,8 +1770,8 @@ gen8_i2c: i2c@c250000 {
#size-cells = <0>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C8
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C8>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;