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ASoC: atmel: mchp-i2s-mcc: Improve maxburst calculation for better performance
The period size represents the size of the DMA descriptor. To ensure all DMA descriptors start from a well-aligned address, the period size must be divided by (sample size * maxburst), not just by maxburst. This adjustment allows for computing a higher maxburst value, thereby increasing the performance of the DMA transfer. Previously, snd_pcm_lib_period_bytes() returned 0 because the runtime HW parameters are computed after the hw_params() callbacks are used. To address this, we now use params_*() functions to compute the period size accurately. This change optimizes the DMA transfer performance by ensuring proper alignment and efficient use of maxburst values. [andrei.simion@microchip.com: Reword commit message and commit title. Add macros with values for maximum DMA chunk size allowed. Add DMA_BURST_ALIGNED preprocessor function to check the alignment of the DMA burst] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Andrei Simion <andrei.simion@microchip.com> Link: https://patch.msgid.link/20240905095633.113784-1-andrei.simion@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -221,6 +221,15 @@
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#define MCHP_I2SMCC_MAX_CHANNELS 8
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#define MCHP_I2MCC_TDM_SLOT_WIDTH 32
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/*
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* ---- DMA chunk size allowed ----
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*/
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#define MCHP_I2SMCC_DMA_8_WORD_CHUNK 8
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#define MCHP_I2SMCC_DMA_4_WORD_CHUNK 4
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#define MCHP_I2SMCC_DMA_2_WORD_CHUNK 2
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#define MCHP_I2SMCC_DMA_1_WORD_CHUNK 1
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#define DMA_BURST_ALIGNED(_p, _s, _w) !(_p % (_s * _w))
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static const struct regmap_config mchp_i2s_mcc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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@ -504,12 +513,30 @@ static int mchp_i2s_mcc_is_running(struct mchp_i2s_mcc_dev *dev)
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return !!(sr & (MCHP_I2SMCC_SR_TXEN | MCHP_I2SMCC_SR_RXEN));
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}
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static inline int mchp_i2s_mcc_period_to_maxburst(int period_size, int sample_size)
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{
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int p_size = period_size;
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int s_size = sample_size;
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if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_8_WORD_CHUNK))
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return MCHP_I2SMCC_DMA_8_WORD_CHUNK;
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if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_4_WORD_CHUNK))
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return MCHP_I2SMCC_DMA_4_WORD_CHUNK;
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if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_2_WORD_CHUNK))
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return MCHP_I2SMCC_DMA_2_WORD_CHUNK;
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return MCHP_I2SMCC_DMA_1_WORD_CHUNK;
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}
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static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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unsigned long rate = 0;
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struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
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int sample_bytes = params_physical_width(params) / 8;
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int period_bytes = params_period_size(params) *
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params_channels(params) * sample_bytes;
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int maxburst;
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u32 mra = 0;
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u32 mrb = 0;
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unsigned int channels = params_channels(params);
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@ -519,9 +546,9 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
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int ret;
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bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
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dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u period_bytes=%d\n",
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__func__, params_rate(params), params_format(params),
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params_width(params), params_channels(params));
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params_width(params), params_channels(params), period_bytes);
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switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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@ -630,11 +657,12 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
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* We must have the same burst size configured
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* in the DMA transfer and in out IP
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*/
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mrb |= MCHP_I2SMCC_MRB_DMACHUNK(channels);
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maxburst = mchp_i2s_mcc_period_to_maxburst(period_bytes, sample_bytes);
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mrb |= MCHP_I2SMCC_MRB_DMACHUNK(maxburst);
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if (is_playback)
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dev->playback.maxburst = 1 << (fls(channels) - 1);
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dev->playback.maxburst = maxburst;
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else
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dev->capture.maxburst = 1 << (fls(channels) - 1);
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dev->capture.maxburst = maxburst;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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