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arm64: dts: apple: t8010: Add cpufreq nodes

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Add cpufreq nodes for Apple A10 SoC. There is a transparent hardware
big.LITTLE switcher in this SoC. Spoof E-core p-state frequencies such
that CPU capacity does not appear to change when switching between core
types.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Nick Chan 2025-02-03 20:43:45 +08:00 committed by Sven Peter
parent b0dfdf02f7
commit 029e1d609a
3 changed files with 102 additions and 0 deletions
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8
arch/arm64/boot/dts/apple/t8010-7.dtsi
View File

@ -45,3 +45,11 @@ switch-mute {
&framebuffer0 {
power-domains = <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>;
};
&hurricane_opp09 {
status = "okay";
};
&hurricane_opp10 {
status = "okay";
};

8
arch/arm64/boot/dts/apple/t8010-ipad6.dtsi
View File

@ -46,3 +46,11 @@ button-volup {
&framebuffer0 {
power-domains = <&ps_disp0_fe &ps_disp0_be &ps_dp>;
};
&hurricane_opp09 {
status = "okay";
};
&hurricane_opp10 {
status = "okay";
};

86
arch/arm64/boot/dts/apple/t8010.dtsi
View File

@ -32,6 +32,8 @@ cpu0: cpu@0 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x0>;
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&fusion_opp>;
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
@ -40,11 +42,89 @@ cpu1: cpu@1 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x1>;
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&fusion_opp>;
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
};
fusion_opp: opp-table {
compatible = "operating-points-v2";
/*
* Apple Fusion Architecture: Hardware big.LITTLE switcher
* that use p-state transitions to switch between cores.
* Only one type of core can be active at a given time.
*
* The E-core frequencies are adjusted so performance scales
* linearly with reported clock speed.
*/
opp01 {
opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
opp-level = <1>;
clock-latency-ns = <11000>;
};
opp02 {
opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
opp-level = <2>;
clock-latency-ns = <49000>;
};
opp03 {
opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
opp-level = <3>;
clock-latency-ns = <13000>;
};
opp04 {
opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
opp-level = <4>;
clock-latency-ns = <18000>;
};
opp05 {
opp-hz = /bits/ 64 <756000000>;
opp-level = <5>;
clock-latency-ns = <35000>;
};
opp06 {
opp-hz = /bits/ 64 <1056000000>;
opp-level = <6>;
clock-latency-ns = <31000>;
};
opp07 {
opp-hz = /bits/ 64 <1356000000>;
opp-level = <7>;
clock-latency-ns = <37000>;
};
opp08 {
opp-hz = /bits/ 64 <1644000000>;
opp-level = <8>;
clock-latency-ns = <39500>;
};
hurricane_opp09: opp09 {
opp-hz = /bits/ 64 <1944000000>;
opp-level = <9>;
clock-latency-ns = <46000>;
status = "disabled"; /* Not available on N112 */
};
hurricane_opp10: opp10 {
opp-hz = /bits/ 64 <2244000000>;
opp-level = <10>;
clock-latency-ns = <56000>;
status = "disabled"; /* Not available on N112 */
};
#if 0
/* Not available until CPU deep sleep is implemented */
hurricane_opp11: opp11 {
opp-hz = /bits/ 64 <2340000000>;
opp-level = <11>;
clock-latency-ns = <56000>;
turbo-mode;
status = "disabled"; /* Not available on N112 */
};
#endif
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@ -52,6 +132,12 @@ soc {
nonposted-mmio;
ranges;
cpufreq: performance-controller@202f20000 {
compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
reg = <0x2 0x02f20000 0 0x1000>;
#performance-domain-cells = <0>;
};
serial0: serial@20a0c0000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x0a0c0000 0x0 0x4000>;