From e25770feb6d60099dcd93f0a9829936398cb4447 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 6 Sep 2022 14:01:34 +0300 Subject: [PATCH 01/30] arm64: tegra: Fix ranges for host1x nodes The currently specified 'ranges' properties don't actually include all devices under the host1x bus on Tegra194 and Tegra234. Expand them appropriately. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 41f3a7e188d0..28740c014f1d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1895,7 +1895,7 @@ host1x@13e00000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0x15000000 0x15000000 0x01000000>; + ranges = <0x14800000 0x14800000 0x02800000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; iommus = <&smmu TEGRA194_SID_HOST1X>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..dcd0224a2a36 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -564,7 +564,7 @@ host1x@13e00000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0x15000000 0x15000000 0x01000000>; + ranges = <0x14800000 0x14800000 0x02000000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; From 68c31ad01105f5cb15f5c863e90fe97a770c951f Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 20 Sep 2022 11:11:59 +0300 Subject: [PATCH 02/30] arm64: tegra: Add NVDEC on Tegra234 Add a device tree node for NVDEC on Tegra234. Booting the firmware requires some information regarding offsets within the firmware binary. These are passed through the device tree, but since the values vary depending on the firmware version, and the firmware itself is not available to the OS, the flasher is expected to provide a device tree overlay with values corresponding to the firmware it is flashing. The overlay then replaces the placeholder values here. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index dcd0224a2a36..35ce8cfb8c08 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -603,6 +603,42 @@ vic@15340000 { iommus = <&smmu_niso1 TEGRA234_SID_VIC>; dma-coherent; }; + + nvdec@15480000 { + compatible = "nvidia,tegra234-nvdec"; + reg = <0x15480000 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVDEC>, + <&bpmp TEGRA234_CLK_FUSE>, + <&bpmp TEGRA234_CLK_TSEC_PKA>; + clock-names = "nvdec", "fuse", "tsec_pka"; + resets = <&bpmp TEGRA234_RESET_NVDEC>; + reset-names = "nvdec"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; + dma-coherent; + + nvidia,memory-controller = <&mc>; + + /* + * Placeholder values that firmware needs to update with the real + * offsets parsed from the microcode headers. + */ + nvidia,bl-manifest-offset = <0>; + nvidia,bl-data-offset = <0>; + nvidia,bl-code-offset = <0>; + nvidia,os-manifest-offset = <0>; + nvidia,os-data-offset = <0>; + nvidia,os-code-offset = <0>; + + /* + * Firmware needs to set this to "okay" once the above values have + * been updated. + */ + status = "disabled"; + }; }; gpio: gpio@2200000 { From 248400656b1cd85de37f3742d065dc1826cdf589 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Wed, 28 Sep 2022 11:57:31 +0530 Subject: [PATCH 03/30] arm64: tegra: Fix Prefetchable aperture ranges of Tegra234 PCIe controllers commit edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against hardware constraints") exposes an issue with the existing partitioning of the aperture space where the Prefetchable apertures of controllers C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint. This patch makes sure that the Prefetchable region doesn't spill over the 32GB boundary. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 35ce8cfb8c08..a1d7b03a6632 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2001,7 +2001,7 @@ pcie@140c0000 { bus-range = <0x0 0xff>; - ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ @@ -2372,7 +2372,7 @@ pcie@141a0000 { bus-range = <0x0 0xff>; - ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ @@ -2478,7 +2478,7 @@ pcie@141e0000 { bus-range = <0x0 0xff>; - ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ From 04491207d2d1e0da6ea7451b958506a76e275c51 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 19 Oct 2022 14:16:13 +0100 Subject: [PATCH 04/30] arm64: tegra: Remove unused property for I2C Commit 156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes") populated the I2C device nodes for Tegra234. One of these nodes contains the property 'nvidia,hw-instance-id' which is neither documented or used. Remove this unused property. Fixes: 156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes") Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index a1d7b03a6632..428b81afc951 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1524,7 +1524,6 @@ gen2_i2c: i2c@c240000 { gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra194-i2c"; reg = <0xc250000 0x100>; - nvidia,hw-instance-id = <0x7>; interrupts = ; status = "disabled"; clock-frequency = <400000>; From 2566d28c4097a500a3d1fb0d8636531e6ded6986 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 19 Oct 2022 14:29:02 +0100 Subject: [PATCH 05/30] arm64: tegra: Populate Tegra234 PWMs Populate all the PWM devices for Tegra234. Finally, update the compatible string for the existing 'pwm1' node to just be 'tegra194-pwm' and remove the fallback to 'tegra186-pwm', which aligns with the binding documentation. Signed-off-by: Jon Hunter Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 80 +++++++++++++++++++++++- 1 file changed, 78 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 428b81afc951..af98d486dd0a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -906,8 +906,7 @@ spi@3270000 { }; pwm1: pwm@3280000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x3280000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; clock-names = "pwm"; @@ -917,6 +916,72 @@ pwm1: pwm@3280000 { #pwm-cells = <2>; }; + pwm2: pwm@3290000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x3290000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM2>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM2>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm3: pwm@32a0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32a0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM3>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM3>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm5: pwm@32c0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32c0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM5>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM5>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm6: pwm@32d0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32d0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM6>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM6>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm7: pwm@32e0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32e0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM7>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM7>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm8: pwm@32f0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32f0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM8>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM8>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + spi@3300000 { compatible = "nvidia,tegra234-qspi"; reg = <0x3300000 0x1000>; @@ -1565,6 +1630,17 @@ gpio_aon: gpio@c2f0000 { gpio-controller; }; + pwm4: pwm@c340000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0xc340000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM4>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM4>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + pmc: pmc@c360000 { compatible = "nvidia,tegra234-pmc"; reg = <0x0c360000 0x10000>, From 7a2c613bdbd83097d5b220b814be0523721d58c4 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 19 Oct 2022 14:29:03 +0100 Subject: [PATCH 06/30] arm64: tegra: Add PWM fan for Jetson AGX Orin Add the PWM fan node for the Tegra234 Jetson AGX Orin platform. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 57ab75328814..f105bdf57ee2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2007,6 +2007,12 @@ serial@3100000 { status = "okay"; }; + pwm@32a0000 { + assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson AGX Orin HDA"; status = "okay"; @@ -2184,4 +2190,12 @@ TEGRA234_AON_GPIO(AA, 4) phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", "p2u-5", "p2u-6", "p2u-7"; }; + + pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + + cooling-levels = <0 95 178 255>; + #cooling-cells = <2>; + }; }; From 1bbba854bc402f7799898a0a5a9f7c9efd07e04b Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 19 Oct 2022 15:47:00 +0100 Subject: [PATCH 07/30] arm64: tegra: Add SBSA UART for Tegra234 Populate the SBSA UART for Tegra234 and enable this UART for Jetson AGX Orin. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 5 +++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index f105bdf57ee2..df703fb0cfff 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2007,6 +2007,11 @@ serial@3100000 { status = "okay"; }; + serial@31d0000 { + current-speed = <115200>; + status = "okay"; + }; + pwm@32a0000 { assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index af98d486dd0a..5f55fdde9a47 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -872,6 +872,13 @@ dp_aux_ch2_i2c: i2c@31c0000 { dma-names = "rx", "tx"; }; + uarti: serial@31d0000 { + compatible = "arm,sbsa-uart"; + reg = <0x31d0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x31e0000 0x100>; From d71b893a119df4ddf63351cffe8557db1cba850f Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Fri, 7 Oct 2022 22:29:41 +0530 Subject: [PATCH 08/30] arm64: tegra: Add Tegra234 SDMMC1 device tree node Add device tree node for Tegra234 SDMMC1 instance. Add and enable SD card instance in device tree. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 7 +++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 56 +++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 9e4d72cfa69f..fe52810e5b9d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -55,6 +55,13 @@ flash@0 { }; }; + mmc@3400000 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>; + disable-wp; + }; + mmc@3460000 { status = "okay"; bus-width = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5f55fdde9a47..73ce043c46a3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra234"; @@ -1003,6 +1004,41 @@ spi@3300000 { status = "disabled"; }; + mmc@3400000 { + compatible = "nvidia,tegra194-sdhci", "nvidia,tegra234-sdhci"; + reg = <0x03400000 0x20000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_SDMMC1>, + <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, + <&bpmp TEGRA234_CLK_PLLC4_MUXED>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, + <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; + resets = <&bpmp TEGRA234_RESET_SDMMC1>; + reset-names = "sdhci"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; + nvidia,default-tap = <14>; + nvidia,default-trim = <0x8>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "disabled"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -1659,6 +1695,26 @@ pmc: pmc@c360000 { #interrupt-cells = <2>; interrupt-controller; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = ; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3-hv"; + power-source = ; + }; }; aon-fabric@c600000 { From 78159542034f42846f0cccb17ff5ca8b82bfda91 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 24 Oct 2022 16:05:16 +0200 Subject: [PATCH 09/30] arm64: tegra: Sort nodes by unit-address The P2U nodes that were recently added were not added in the correct order. Sort them in the right place by unit-address. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 384 +++++++++++------------ 1 file changed, 192 insertions(+), 192 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 73ce043c46a3..78e0df6ba56f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1111,6 +1111,198 @@ hsp_top0: hsp@3c00000 { #mbox-cells = <2>; }; + p2u_hsio_0: phy@3e00000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e00000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_1: phy@3e10000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_2: phy@3e20000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_3: phy@3e30000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_4: phy@3e40000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_5: phy@3e50000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e50000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_6: phy@3e60000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e60000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_7: phy@3e70000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e70000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_0: phy@3e90000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e90000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_1: phy@3ea0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ea0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_2: phy@3eb0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03eb0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_3: phy@3ec0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ec0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_4: phy@3ed0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ed0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_5: phy@3ee0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ee0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_6: phy@3ef0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ef0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_7: phy@3f00000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f00000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_0: phy@3f20000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_1: phy@3f30000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_2: phy@3f40000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_3: phy@3f50000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f50000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_4: phy@3f60000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f60000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_5: phy@3f70000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f70000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_6: phy@3f80000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f80000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_7: phy@3f90000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f90000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + ethernet@6800000 { compatible = "nvidia,tegra234-mgbe"; reg = <0x06800000 0x10000>, @@ -1403,198 +1595,6 @@ rce-fabric@be00000 { status = "okay"; }; - p2u_hsio_0: phy@3e00000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e00000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_1: phy@3e10000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e10000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_2: phy@3e20000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_3: phy@3e30000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_4: phy@3e40000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_5: phy@3e50000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e50000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_6: phy@3e60000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e60000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_7: phy@3e70000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e70000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_0: phy@3e90000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e90000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_1: phy@3ea0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ea0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_2: phy@3eb0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03eb0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_3: phy@3ec0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ec0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_4: phy@3ed0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ed0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_5: phy@3ee0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ee0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_6: phy@3ef0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ef0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_7: phy@3f00000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f00000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_0: phy@3f20000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_1: phy@3f30000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_2: phy@3f40000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_3: phy@3f50000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f50000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_4: phy@3f60000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f60000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_5: phy@3f70000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f70000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_6: phy@3f80000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f80000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_7: phy@3f90000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f90000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; From 58bf48a25af13421e12dc854fef6560f8b3eadf7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 24 Oct 2022 16:05:57 +0200 Subject: [PATCH 10/30] arm64: tegra: Add missing whitespace The unit-address of a node should be separated from the opening brace by a space. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 78e0df6ba56f..f7834753ce64 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1750,7 +1750,7 @@ gic: interrupt-controller@f400000 { interrupt-controller; }; - smmu_iso: iommu@10000000{ + smmu_iso: iommu@10000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; reg = <0x10000000 0x1000000>; interrupts = , From daf92599762a658a9f65eae9e6c19db5bf3c2543 Mon Sep 17 00:00:00 2001 From: Sandipan Patra Date: Mon, 19 Sep 2022 19:44:55 +0530 Subject: [PATCH 11/30] arm64: tegra: Enable PWM users on Jetson AGX Orin Enable additional PWM controllers in device tree so that the PWM pins on the Jetson AGX Orin Developer Kit 40-pin header can be used. Signed-off-by: Sandipan Patra Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi index a85993c85e45..e76894574d32 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -2,4 +2,18 @@ / { compatible = "nvidia,p3737-0000"; + + bus@0 { + pwm@3280000 { + status = "okay"; + }; + + pwm@32c0000 { + status = "okay"; + }; + + pwm@32f0000 { + status = "okay"; + }; + }; }; From 501c9e7ca66bfd6a98f5fceac6a1aaa5eb9507ed Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Oct 2022 13:35:56 +0100 Subject: [PATCH 12/30] arm64: tegra: Update console for Jetson Xavier and Orin The Tegra Combined UART (TCU) is the default serial interface for Jetson Xavier and Orin platforms and so update the bootargs for these platforms to use the TCU. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index b0f9393dd39c..cd272d407e01 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -23,7 +23,7 @@ aliases { }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyTCU0,115200n8"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index 0bd66f9c620b..0751edddf7d5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -20,7 +20,7 @@ aliases { }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyTCU0,115200n8"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index df703fb0cfff..96aa2267b06d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2025,7 +2025,7 @@ hda@3510000 { }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyTCU0,115200n8"; stdout-path = "serial0:115200n8"; }; From 8fbd2d118917381c9d3247d6ae03f3b7d7d7604d Mon Sep 17 00:00:00 2001 From: Dipen Patel Date: Thu, 3 Nov 2022 10:45:22 -0700 Subject: [PATCH 13/30] arm64: tegra: Enable GTE nodes Add and enable AON and LIC GTE nodes by default. Signed-off-by: Dipen Patel Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 28740c014f1d..935c85e2095c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1366,6 +1366,16 @@ cec@3960000 { status = "disabled"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra194-gte-lic"; + reg = <0x3aa0000 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,slices = <11>; + #timestamp-cells = <1>; + status = "okay"; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; @@ -1579,6 +1589,16 @@ hsp_aon: hsp@c150000 { #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra194-gte-aon"; + reg = <0xc1e0000 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,slices = <3>; + #timestamp-cells = <1>; + status = "okay"; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0c240000 0x10000>; From b6e097df67df38b8699f26ccc9d5be97831cb3d2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 12:43:49 +0100 Subject: [PATCH 14/30] arm64: tegra: Remove clock-names from PWM nodes The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property. Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 -------- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 8 -------- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 -------- 4 files changed, 25 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6602fe421ee8..bd4a099fca01 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -790,7 +790,6 @@ pwm1: pwm@3280000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x3280000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM1>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; @@ -801,7 +800,6 @@ pwm2: pwm@3290000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x3290000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM2>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM2>; reset-names = "pwm"; status = "disabled"; @@ -812,7 +810,6 @@ pwm3: pwm@32a0000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32a0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM3>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM3>; reset-names = "pwm"; status = "disabled"; @@ -823,7 +820,6 @@ pwm5: pwm@32c0000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32c0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM5>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM5>; reset-names = "pwm"; status = "disabled"; @@ -834,7 +830,6 @@ pwm6: pwm@32d0000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32d0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM6>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM6>; reset-names = "pwm"; status = "disabled"; @@ -845,7 +840,6 @@ pwm7: pwm@32e0000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32e0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM7>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM7>; reset-names = "pwm"; status = "disabled"; @@ -856,7 +850,6 @@ pwm8: pwm@32f0000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32f0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM8>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM8>; reset-names = "pwm"; status = "disabled"; @@ -1274,7 +1267,6 @@ pwm4: pwm@c340000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0xc340000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM4>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM4>; reset-names = "pwm"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 935c85e2095c..7c9801a03506 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -958,7 +958,6 @@ pwm1: pwm@3280000 { "nvidia,tegra186-pwm"; reg = <0x3280000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM1>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; @@ -970,7 +969,6 @@ pwm2: pwm@3290000 { "nvidia,tegra186-pwm"; reg = <0x3290000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM2>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM2>; reset-names = "pwm"; status = "disabled"; @@ -982,7 +980,6 @@ pwm3: pwm@32a0000 { "nvidia,tegra186-pwm"; reg = <0x32a0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM3>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM3>; reset-names = "pwm"; status = "disabled"; @@ -994,7 +991,6 @@ pwm5: pwm@32c0000 { "nvidia,tegra186-pwm"; reg = <0x32c0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM5>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM5>; reset-names = "pwm"; status = "disabled"; @@ -1006,7 +1002,6 @@ pwm6: pwm@32d0000 { "nvidia,tegra186-pwm"; reg = <0x32d0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM6>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM6>; reset-names = "pwm"; status = "disabled"; @@ -1018,7 +1013,6 @@ pwm7: pwm@32e0000 { "nvidia,tegra186-pwm"; reg = <0x32e0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM7>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM7>; reset-names = "pwm"; status = "disabled"; @@ -1030,7 +1024,6 @@ pwm8: pwm@32f0000 { "nvidia,tegra186-pwm"; reg = <0x32f0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM8>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM8>; reset-names = "pwm"; status = "disabled"; @@ -1687,7 +1680,6 @@ pwm4: pwm@c340000 { "nvidia,tegra186-pwm"; reg = <0xc340000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM4>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM4>; reset-names = "pwm"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 724e87450605..0cdad97b6962 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -667,7 +667,6 @@ pwm: pwm@7000a000 { reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA210_CLK_PWM>; - clock-names = "pwm"; resets = <&tegra_car 17>; reset-names = "pwm"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f7834753ce64..8fc77f3a2cc6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -917,7 +917,6 @@ pwm1: pwm@3280000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x3280000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; @@ -928,7 +927,6 @@ pwm2: pwm@3290000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x3290000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM2>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM2>; reset-names = "pwm"; status = "disabled"; @@ -939,7 +937,6 @@ pwm3: pwm@32a0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x32a0000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM3>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM3>; reset-names = "pwm"; status = "disabled"; @@ -950,7 +947,6 @@ pwm5: pwm@32c0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x32c0000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM5>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM5>; reset-names = "pwm"; status = "disabled"; @@ -961,7 +957,6 @@ pwm6: pwm@32d0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x32d0000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM6>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM6>; reset-names = "pwm"; status = "disabled"; @@ -972,7 +967,6 @@ pwm7: pwm@32e0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x32e0000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM7>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM7>; reset-names = "pwm"; status = "disabled"; @@ -983,7 +977,6 @@ pwm8: pwm@32f0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x32f0000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM8>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM8>; reset-names = "pwm"; status = "disabled"; @@ -1677,7 +1670,6 @@ pwm4: pwm@c340000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0xc340000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM4>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM4>; reset-names = "pwm"; status = "disabled"; From 794b834d4cd3fa05e1b4476c46dc64a6b21cf4d4 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Mon, 14 Nov 2022 15:53:33 +0000 Subject: [PATCH 15/30] arm64: tegra: Add ECAM aperture info for all the PCIe controllers Add the ECAM aperture information for all the PCIe controllers of Tegra234. Signed-off-by: Vidya Sagar Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 55 ++++++++++++++---------- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8fc77f3a2cc6..22dc93a326f0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2045,8 +2045,9 @@ pcie@140a0000 { reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2098,8 +2099,9 @@ pcie@140c0000 { reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2151,8 +2153,9 @@ pcie@140e0000 { reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2204,8 +2207,9 @@ pcie@14100000 { reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2257,8 +2261,9 @@ pcie@14120000 { reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2310,8 +2315,9 @@ pcie@14140000 { reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2363,8 +2369,9 @@ pcie@14160000 { reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2416,8 +2423,9 @@ pcie@14180000 { reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2469,8 +2477,9 @@ pcie@141a0000 { reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2522,8 +2531,9 @@ pcie@141c0000 { reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2575,8 +2585,9 @@ pcie@141e0000 { reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; From 6f380a4ec04fc97d7f006f525fd7ece0b2bfe238 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 15:23:45 +0100 Subject: [PATCH 16/30] arm64: tegra: Separate AON pinmux from main pinmux on Tegra194 The registers for the AON pinmux reside in a partition different from the registers for the main pinmux. Instead of treating them as one and the same device, split them up so that they are each their own devices. Also add gpio-ranges properties to the corresponding GPIO controllers such that the pinmux and GPIO controllers can be paired up properly. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 7c9801a03506..c6c10580e664 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -86,6 +86,7 @@ gpio: gpio@2200000 { interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux 0 0 169>; }; cbb-noc@2300000 { @@ -626,9 +627,7 @@ tegra_asrc: asrc@2910000 { pinmux: pinmux@2430000 { compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000>, - <0xc300000 0x4000>; - + reg = <0x2430000 0x17000>; status = "okay"; pex_rst_c5_out_state: pex_rst_c5_out { @@ -1673,6 +1672,14 @@ gpio_aon: gpio@c2f0000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-range = <&pinmux_aon 0 0 30>; + }; + + pinmux_aon: pinmux@c300000 { + compatible = "nvidia,tegra194-pinmux-aon"; + reg = <0xc300000 0x4000>; + + status = "okay"; }; pwm4: pwm@c340000 { From b8f44643d68cdf64cebc42d276b5e4094f98a01f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 3 Nov 2022 12:35:48 +0100 Subject: [PATCH 17/30] arm64: tegra: Add missing compatible string to Ethernet USB device According to the DT schema in usb-device.yaml, each USB device node needs a compatible string, so add one for the built-in USB Ethernet device on Jetson TX1. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a44c56c1e56e..4286e04e685c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1368,6 +1368,7 @@ usb@70090000 { #size-cells = <0>; ethernet@1 { + compatible = "usb955,9ff"; reg = <1>; }; }; From 47a2f35d9ea76d92aa2385671f527b75aa9dfe45 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Tue, 25 Oct 2022 23:55:08 +0530 Subject: [PATCH 18/30] arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller Fix the starting address of the non-prefetchable aperture of PCIe C3 controller. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 22dc93a326f0..aa278f565eea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2350,7 +2350,7 @@ pcie@14140000 { bus-range = <0x0 0xff>; ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, From dd0be8278ab9675d168390c990110f8d2f62ca38 Mon Sep 17 00:00:00 2001 From: Akhil R Date: Thu, 10 Nov 2022 22:47:47 +0530 Subject: [PATCH 19/30] arm64: tegra: Add dma-channel-mask in GPCDMA node Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index bd4a099fca01..b3f1494c02c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -78,7 +78,8 @@ gpcdma: dma-controller@2600000 { reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA186_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -112,6 +113,7 @@ gpcdma: dma-controller@2600000 { #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c6c10580e664..a6721bb82bbd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -143,7 +143,8 @@ gpcdma: dma-controller@2600000 { reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA194_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -177,6 +178,7 @@ gpcdma: dma-controller@2600000 { #dma-cells = <1>; iommus = <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aa278f565eea..97d47327afdd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -28,7 +28,8 @@ gpcdma: dma-controller@2600000 { reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -61,6 +62,7 @@ gpcdma: dma-controller@2600000 { ; #dma-cells = <1>; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-channel-mask = <0xfffffffe>; dma-coherent; }; From 14910d68718cae5f287c95997dcc9a99531109d6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 19 Sep 2022 07:43:50 -0300 Subject: [PATCH 20/30] arm64: tegra: Remove 'enable-active-low' The 'enable-active-low' property is not a valid one. Only 'enable-active-high' is valid, and when this property is absent the gpio regulator will act as active low by default. Remove the invalid 'enable-active-low' property. Signed-off-by: Fabio Estevam Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index fe52810e5b9d..8b86ea9cb50c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -39,7 +39,6 @@ vdd_12v_pcie: regulator-vdd-12v-pcie { regulator-max-microvolt = <12000000>; gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; regulator-boot-on; - enable-active-low; }; bus@0 { From 27f1568b1d5fe35014074f92717b250afbe67031 Mon Sep 17 00:00:00 2001 From: Pierre Gondois Date: Mon, 7 Nov 2022 16:57:08 +0100 Subject: [PATCH 21/30] arm64: tegra: Update cache properties The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 ++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a6721bb82bbd..e64b4a048efd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -3050,36 +3050,51 @@ core1 { }; l2c_0: l2-cache0 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_1: l2-cache1 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_2: l2-cache2 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_3: l2-cache3 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l3c: l3-cache { + compatible = "cache"; + cache-unified; cache-size = <4194304>; cache-line-size = <64>; + cache-level = <3>; cache-sets = <4096>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0cdad97b6962..046ce8ebd505 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2004,6 +2004,7 @@ CPU_SLEEP: cpu-sleep { L2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 97d47327afdd..8baeed783903 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3084,117 +3084,150 @@ core3 { }; l2c0_0: l2-cache00 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_1: l2-cache01 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_2: l2-cache02 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_3: l2-cache03 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c1_0: l2-cache10 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_1: l2-cache11 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_2: l2-cache12 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_3: l2-cache13 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c2_0: l2-cache20 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_1: l2-cache21 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_2: l2-cache22 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_3: l2-cache23 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l3c0: l3-cache0 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c1: l3-cache1 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c2: l3-cache2 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; }; From 85ab13c184dcc4dbd70552376fc9c1bc47d8e1d9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 7 Dec 2021 15:03:41 +0100 Subject: [PATCH 22/30] arm64: tegra: Restructure Tegra210 PMC pinmux nodes The PMC pinmux configuration nodes need to be part of a top-level pinmux node. Add that new "pinmux" node and move the configuration nodes into it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 40 +++++++++++------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 046ce8ebd505..e2d84335ec82 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -911,35 +911,33 @@ pd_venc: venc { }; }; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = ; - }; + pinmux { + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1"; + power-source = ; + }; - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = ; - }; + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1"; + power-source = ; + }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3"; - power-source = ; - }; + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3"; + power-source = ; + }; - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3"; - power-source = ; - }; + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3"; + power-source = ; + }; - pex_dpd_disable: pex_en { - pex-dpd-disable { + pex_dpd_disable: pex-dpd-disable { pins = "pex-bias", "pex-clk1", "pex-clk2"; low-power-disable; }; - }; - pex_dpd_enable: pex_dis { - pex-dpd-enable { + pex_dpd_enable: pex-dpd-enable { pins = "pex-bias", "pex-clk1", "pex-clk2"; low-power-enable; }; From 3d5d63e96af46a3658272bcd25ba4c20997d19b9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 14:10:17 +0100 Subject: [PATCH 23/30] arm64: tegra: Use vbus-gpios property Instead of using the deprecated vbus-gpio property, switch to using the more standard vbus-gpios property. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 273a1ef716b6..f212f6aced04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2117,8 +2117,8 @@ connector { "usb-b-connector"; label = "micro-USB"; type = "micro"; - vbus-gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) - GPIO_ACTIVE_LOW>; + vbus-gpios = <&gpio TEGRA194_MAIN_GPIO(Z, 1) + GPIO_ACTIVE_LOW>; }; }; From 7f0ea5acfc195076a0a4042d18a4abd18a080772 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 14:11:04 +0100 Subject: [PATCH 24/30] arm64: tegra: Use correct compatible string for Tegra194 HDA The Tegra194 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index e64b4a048efd..1db0737801a7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1148,7 +1148,7 @@ sdmmc4: mmc@3460000 { }; hda@3510000 { - compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; + compatible = "nvidia,tegra194-hda"; reg = <0x3510000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_HDA>, From b2fbcbe1ae1946d2aae47fac02a2547c6475fffa Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 14:14:16 +0100 Subject: [PATCH 25/30] arm64: tegra: Use correct compatible string for Tegra234 HDA The Tegra234 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8baeed783903..2e39b4bccda0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1064,7 +1064,7 @@ mmc@3460000 { }; hda@3510000 { - compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; + compatible = "nvidia,tegra234-hda"; reg = <0x3510000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, From e9ddebc3a210f434f69ec7e68dd857b8af3b8300 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 5 Sep 2022 18:08:55 +0200 Subject: [PATCH 26/30] arm64: tegra: Remove reset-names for QSPI The Tegra QSPI controllers use a single reset control, so reset-names is not necessary and therefore not specified in the DT bindings. Drop the property from device tree files to avoid validation warnings. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 1db0737801a7..81a2ab56810f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -936,7 +936,6 @@ spi@3270000 { <&bpmp TEGRA194_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA194_RESET_QSPI0>; - reset-names = "qspi"; status = "disabled"; }; @@ -950,7 +949,6 @@ spi@3300000 { <&bpmp TEGRA194_CLK_QSPI1_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA194_RESET_QSPI1>; - reset-names = "qspi"; status = "disabled"; }; From efe499d8854f73686c6ebc1c89b33d8ee4a30181 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 13:35:08 +0100 Subject: [PATCH 27/30] arm64: tegra: Fixup pinmux node names Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 4 ++-- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 18 ++++++++++++------ 5 files changed, 19 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index d461da0b8049..3e8dee85d55f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -62,7 +62,7 @@ pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; - pinmux_default: pinmux@0 { + pinmux_default: pinmux { dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 81a2ab56810f..4afcbd60e144 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -632,7 +632,7 @@ pinmux: pinmux@2430000 { reg = <0x2430000 0x17000>; status = "okay"; - pex_rst_c5_out_state: pex_rst_c5_out { + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = ; @@ -643,7 +643,7 @@ pex_rst { }; }; - clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { + clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { clkreq { nvidia,pins = "pex_l5_clkreq_n_pgg0"; nvidia,schmitt = ; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 4286e04e685c..dd9a17922fe5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1293,14 +1293,14 @@ shutdown { }; }; - dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_active_state: pinmux-dvfs-pwm-active { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = ; }; }; - dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = ; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 37678c337a34..2041371ea7ff 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -109,14 +109,14 @@ gpu@57000000 { }; pinmux@700008d4 { - dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_active_state: pinmux-dvfs-pwm-active { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = ; }; }; - dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = ; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index e2d84335ec82..92c03ef623da 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -554,42 +554,48 @@ pinmux: pinmux@700008d4 { compatible = "nvidia,tegra210-pinmux"; reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ <0x0 0x70003000 0x0 0x294>; /* Mux registers */ - sdmmc1_3v3_drv: sdmmc1-3v3-drv { + + sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; nvidia,pull-down-strength = <0x8>; nvidia,pull-up-strength = <0x8>; }; }; - sdmmc1_1v8_drv: sdmmc1-1v8-drv { + + sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; nvidia,pull-down-strength = <0x4>; nvidia,pull-up-strength = <0x3>; }; }; - sdmmc2_1v8_drv: sdmmc2-1v8-drv { + + sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { sdmmc2 { nvidia,pins = "drive_sdmmc2"; nvidia,pull-down-strength = <0x10>; nvidia,pull-up-strength = <0x10>; }; }; - sdmmc3_3v3_drv: sdmmc3-3v3-drv { + + sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; nvidia,pull-down-strength = <0x8>; nvidia,pull-up-strength = <0x8>; }; }; - sdmmc3_1v8_drv: sdmmc3-1v8-drv { + + sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; nvidia,pull-down-strength = <0x4>; nvidia,pull-up-strength = <0x3>; }; }; - sdmmc4_1v8_drv: sdmmc4-1v8-drv { + + sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { sdmmc4 { nvidia,pins = "drive_sdmmc4"; nvidia,pull-down-strength = <0x10>; From d8e194786a89ac3c9f7657e97eb38a2238519bd3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 13:35:57 +0100 Subject: [PATCH 28/30] arm64: tegra: Remove unused reset-names for QSPI The Tegra QSPI controller uses a single reset line, so there's no need for a reset-names property. Remove such properties. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 92c03ef623da..bc0cacb20d7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1868,7 +1868,6 @@ spi@70410000 { <&tegra_car TEGRA210_CLK_QSPI_PM>; clock-names = "qspi", "qspi_out"; resets = <&tegra_car 211>; - reset-names = "qspi"; dmas = <&apbdma 5>, <&apbdma 5>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 2e39b4bccda0..e3630d6300c4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -911,7 +911,6 @@ spi@3270000 { <&bpmp TEGRA234_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI0>; - reset-names = "qspi"; status = "disabled"; }; @@ -995,7 +994,6 @@ spi@3300000 { <&bpmp TEGRA234_CLK_QSPI1_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI1>; - reset-names = "qspi"; status = "disabled"; }; From 132b552cba159f41b576fbd0da8e0684460f9ab3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 13:38:34 +0100 Subject: [PATCH 29/30] arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234 The compatible string list for SDHCI on Tegra234 should be "nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci" fallback. Use that consistently for all SDHCI controllers. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index e3630d6300c4..eaf05ee9acd1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -998,7 +998,7 @@ spi@3300000 { }; mmc@3400000 { - compatible = "nvidia,tegra194-sdhci", "nvidia,tegra234-sdhci"; + compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03400000 0x20000>; interrupts = ; clocks = <&bpmp TEGRA234_CLK_SDMMC1>, From 1002a361127b6b42b8d1ef686a4c1fa68541d6f5 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Nov 2022 09:32:41 +0100 Subject: [PATCH 30/30] arm64: tegra: Remove unneeded clock-names for Tegra132 PWM There's only a single clock for this IP block, so it doesn't need a clock-names property. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 3673f79adf1a..858fc01cecb6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -393,7 +393,6 @@ pwm: pwm@7000a000 { reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA124_CLK_PWM>; - clock-names = "pwm"; resets = <&tegra_car 17>; reset-names = "pwm"; status = "disabled";