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drm/amd/display: Optimize cursor position updates

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[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.

[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if there is no change to it.  This removes the
read-modify-write from the cursor position programming path in HUBP and
DPP, leaving only the register writes.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Sung Lee <sung.lee@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aric Cyr 2024-12-10 18:38:15 -05:00 committed by Alex Deucher
parent 01130f5260
commit 024771f3fb
4 changed files with 19 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
View File

@ -483,10 +483,11 @@ void dpp1_set_cursor_position(
if (src_y_offset + cursor_height <= 0)
cur_en = 0; /* not visible beyond top edge*/
REG_UPDATE(CURSOR0_CONTROL,
CUR0_ENABLE, cur_en);
if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
}
}
void dpp1_cnv_set_optional_cursor_attributes(

6
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
View File

@ -154,9 +154,11 @@ void dpp401_set_cursor_position(
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
uint32_t cur_en = pos->enable ? 1 : 0;
REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
}
}
void dpp401_set_optional_cursor_attributes(

8
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
View File

@ -1058,11 +1058,13 @@ void hubp2_cursor_set_position(
if (src_y_offset + cursor_height <= 0)
cur_en = 0; /* not visible beyond top edge*/
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
REG_UPDATE(CURSOR_CONTROL,
REG_UPDATE(CURSOR_CONTROL,
CURSOR_ENABLE, cur_en);
}
REG_SET_2(CURSOR_POSITION, 0,
CURSOR_X_POSITION, pos->x,

10
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
View File

@ -742,11 +742,13 @@ void hubp401_cursor_set_position(
dc_fixpt_from_int(dst_x_offset),
param->h_scale_ratio));
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
REG_UPDATE(CURSOR_CONTROL,
CURSOR_ENABLE, cur_en);
REG_UPDATE(CURSOR_CONTROL,
CURSOR_ENABLE, cur_en);
}
REG_SET_2(CURSOR_POSITION, 0,
CURSOR_X_POSITION, x_pos,