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riscv: Add xtheadvector instruction definitions

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xtheadvector uses different encodings than standard vector for
vsetvli and vector loads/stores. Write the instruction formats to be
used in assembly code.

Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-8-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Charlie Jenkins 2024-11-13 18:21:14 -08:00 committed by Palmer Dabbelt
parent b9a9314424
commit 01e3313e34
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1 changed files with 25 additions and 0 deletions
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25
arch/riscv/include/asm/vendor_extensions/thead.h
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@ -19,4 +19,29 @@ void disable_xtheadvector(void);
static inline void disable_xtheadvector(void) { }
#endif
/* Extension specific helpers */
/*
* Vector 0.7.1 as used for example on T-Head Xuantie cores, uses an older
* encoding for vsetvli (ta, ma vs. d1), so provide an instruction for
* vsetvli t4, x0, e8, m8, d1
*/
#define THEAD_VSETVLI_T4X0E8M8D1 ".long 0x00307ed7\n\t"
/*
* While in theory, the vector-0.7.1 vsb.v and vlb.v result in the same
* encoding as the standard vse8.v and vle8.v, compilers seem to optimize
* the call resulting in a different encoding and then using a value for
* the "mop" field that is not part of vector-0.7.1
* So encode specific variants for vstate_save and _restore.
*/
#define THEAD_VSB_V_V0T0 ".long 0x02028027\n\t"
#define THEAD_VSB_V_V8T0 ".long 0x02028427\n\t"
#define THEAD_VSB_V_V16T0 ".long 0x02028827\n\t"
#define THEAD_VSB_V_V24T0 ".long 0x02028c27\n\t"
#define THEAD_VLB_V_V0T0 ".long 0x012028007\n\t"
#define THEAD_VLB_V_V8T0 ".long 0x012028407\n\t"
#define THEAD_VLB_V_V16T0 ".long 0x012028807\n\t"
#define THEAD_VLB_V_V24T0 ".long 0x012028c07\n\t"
#endif