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intel-pinctrl for v7.0-2
* Fix 1kOhm, debounce, and PWM capability support * Add support for new PAD_OWN layout -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmnNGOYACgkQb7wzTHR8 rCiJlA/9Eb+VhUlGoMxL52086zmcPqvfAFSTHs+hrnKDtnEICFdGniqefZx88+TR v07O0pJC1c545WEHgo92Idg8nJY6BuKBz0yALLgsd1qqZRigg3a/6mnIHUvTO82f f5pKSJo1WGlc7Re177nAk55vcbwqbefbWFO89gfzsveOMwNYhOnAfYYN4JQaMM0p M3WPwsLzUEgunnzALLn60VReHg3aWp5h7+FoM1UkY+asAhfAQ1IiWcAf/HhHjGar DtgpAPE6CDjO2cLqyF2ky9TOKTnkqjX3CxFplIhdnVHblAlp2z096aIiJV3xH5Pk uN1WLsvj7LYowlBhBrh/UZjZ0XJbTi3/DgTG4EcqvEzPzG3wDfvO8B9DTg5RP1N0 Q29rxi9OshaZ82JpJMn9TDClFdJCmUmx7cFlZTqH9ZjQ3CJhgQUkWGXtLXJUKkJt SReRFMMX77UXeqXBQF0RuI+OzD3jqtUPFRRrA7NdsKrY7f2AZ0dstq8MA9xXt7T0 ekNgRIH/5FoUJFF389ZYsEgOUmhU12SQ3BO4TSnpxlXOvxJiAf5mfnhgbrKSNUbC CQJZc2ObGoaPi5u9VcQzXRTTenNetdPQkpyo7sHYTikekRxVsTw/VQKiY5n17USK l8zZ7beE9kbRGsNq2zt13Ro0aTwrSHf2CcswwP24zDsU7Dxe5Qg= =Ob1Q -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v7.0-2 * Fix 1kOhm, debounce, and PWM capability support * Add support for new PAD_OWN layout Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
commit
01c3ec507a
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@ -53,8 +53,6 @@
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#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
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#define PADOWN_GPP(p) ((p) / 8)
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#define PWMC 0x204
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/* Offset from pad_regs */
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#define PADCFG0 0x000
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#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
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@ -205,19 +203,25 @@ static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned
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community = intel_get_community(pctrl, pin);
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if (!community)
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return false;
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if (!community->padown_offset)
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/* If padown_offset is not provided, assume host ownership */
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padown = community->regs + community->padown_offset;
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if (padown == community->regs)
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return true;
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/* New HW generations have extended PAD_OWN registers */
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if (community->features & PINCTRL_FEATURE_3BIT_PAD_OWN)
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return !(readl(padown + pin_to_padno(community, pin) * 4) & 7);
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padgrp = intel_community_get_padgroup(community, pin);
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if (!padgrp)
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return false;
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gpp_offset = padgroup_offset(padgrp, pin);
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gpp = PADOWN_GPP(gpp_offset);
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offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
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padown = community->regs + offset;
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offset = padgrp->padown_num * 4 + gpp * 4;
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return !(readl(padown) & PADOWN_MASK(gpp_offset));
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return !(readl(padown + offset) & PADOWN_MASK(gpp_offset));
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}
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static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin)
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@ -1549,8 +1553,10 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
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}
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static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
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struct intel_community *community)
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struct intel_community *community,
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unsigned short capability_offset)
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{
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void __iomem *base = community->regs + capability_offset + 4;
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static const struct pwm_lpss_boardinfo info = {
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.clk_rate = 19200000,
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.npwm = 1,
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@ -1564,7 +1570,7 @@ static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
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if (!IS_REACHABLE(CONFIG_PWM_LPSS))
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return 0;
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chip = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
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chip = devm_pwm_lpss_probe(pctrl->dev, base, &info);
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return PTR_ERR_OR_ZERO(chip);
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}
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@ -1595,7 +1601,9 @@ int intel_pinctrl_probe(struct platform_device *pdev,
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for (i = 0; i < pctrl->ncommunities; i++) {
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struct intel_community *community = &pctrl->communities[i];
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unsigned short capability_offset[6];
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void __iomem *regs;
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u32 revision;
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u32 offset;
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u32 value;
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@ -1610,10 +1618,14 @@ int intel_pinctrl_probe(struct platform_device *pdev,
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value = readl(regs + REVID);
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if (value == ~0u)
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return -ENODEV;
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if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
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revision = (value & REVID_MASK) >> REVID_SHIFT;
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if (revision >= 0x092) {
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community->features |= PINCTRL_FEATURE_DEBOUNCE;
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community->features |= PINCTRL_FEATURE_1K_PD;
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}
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if (revision >= 0x110)
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community->features |= PINCTRL_FEATURE_3BIT_PAD_OWN;
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/* Determine community features based on the capabilities */
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offset = CAPLIST;
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@ -1622,15 +1634,19 @@ int intel_pinctrl_probe(struct platform_device *pdev,
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switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
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case CAPLIST_ID_GPIO_HW_INFO:
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community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
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capability_offset[CAPLIST_ID_GPIO_HW_INFO] = offset;
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break;
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case CAPLIST_ID_PWM:
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community->features |= PINCTRL_FEATURE_PWM;
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capability_offset[CAPLIST_ID_PWM] = offset;
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break;
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case CAPLIST_ID_BLINK:
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community->features |= PINCTRL_FEATURE_BLINK;
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capability_offset[CAPLIST_ID_BLINK] = offset;
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break;
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case CAPLIST_ID_EXP:
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community->features |= PINCTRL_FEATURE_EXP;
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capability_offset[CAPLIST_ID_EXP] = offset;
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break;
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default:
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break;
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@ -1653,7 +1669,7 @@ int intel_pinctrl_probe(struct platform_device *pdev,
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if (ret)
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return ret;
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ret = intel_pinctrl_probe_pwm(pctrl, community);
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ret = intel_pinctrl_probe_pwm(pctrl, community, capability_offset[CAPLIST_ID_PWM]);
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if (ret)
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return ret;
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}
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@ -150,6 +150,7 @@ struct intel_community {
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#define PINCTRL_FEATURE_PWM BIT(3)
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#define PINCTRL_FEATURE_BLINK BIT(4)
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#define PINCTRL_FEATURE_EXP BIT(5)
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#define PINCTRL_FEATURE_3BIT_PAD_OWN BIT(6)
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#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \
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{ \
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