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arm64: Unconditionally enable PAN support
FEAT_PAN has been around since ARMv8.1 (over 11 years ago), has no compiler dependency (we have our own accessors), and is a great security benefit. Drop CONFIG_ARM64_PAN, and make the support unconditionnal. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
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@ -1680,7 +1680,6 @@ config MITIGATE_SPECTRE_BRANCH_HISTORY
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config ARM64_SW_TTBR0_PAN
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bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
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depends on !KCSAN
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select ARM64_PAN
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help
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Enabling this option prevents the kernel from accessing
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user-space memory directly by pointing TTBR0_EL1 to a reserved
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@ -1859,20 +1858,6 @@ config ARM64_HW_AFDBM
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to work on pre-ARMv8.1 hardware and the performance impact is
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minimal. If unsure, say Y.
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config ARM64_PAN
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bool "Enable support for Privileged Access Never (PAN)"
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default y
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help
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Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
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prevents the kernel or hypervisor from accessing user-space (EL0)
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memory directly.
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Choosing this option will cause any unprotected (not using
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copy_to_user et al) memory access to fail with a permission fault.
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The feature is detected at runtime, and will remain as a 'nop'
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instruction if the cpu does not implement the feature.
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endmenu # "ARMv8.1 architectural features"
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menu "ARMv8.2 architectural features"
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@ -2109,7 +2094,6 @@ config ARM64_MTE
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depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
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depends on AS_HAS_ARMV8_5
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# Required for tag checking in the uaccess routines
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select ARM64_PAN
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select ARCH_HAS_SUBPAGE_FAULTS
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select ARCH_USES_HIGH_VMA_FLAGS
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select ARCH_USES_PG_ARCH_2
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@ -2141,7 +2125,6 @@ menu "ARMv8.7 architectural features"
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config ARM64_EPAN
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bool "Enable support for Enhanced Privileged Access Never (EPAN)"
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default y
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depends on ARM64_PAN
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help
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Enhanced Privileged Access Never (EPAN) allows Privileged
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Access Never to be used with Execute-only mappings.
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@ -19,8 +19,6 @@ cpucap_is_possible(const unsigned int cap)
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"cap must be < ARM64_NCAPS");
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switch (cap) {
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case ARM64_HAS_PAN:
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return IS_ENABLED(CONFIG_ARM64_PAN);
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case ARM64_HAS_EPAN:
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return IS_ENABLED(CONFIG_ARM64_EPAN);
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case ARM64_SVE:
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@ -124,14 +124,12 @@ static inline bool uaccess_ttbr0_enable(void)
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static inline void __uaccess_disable_hw_pan(void)
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{
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asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN,
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CONFIG_ARM64_PAN));
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asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN));
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}
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static inline void __uaccess_enable_hw_pan(void)
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{
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asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,
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CONFIG_ARM64_PAN));
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asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN));
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}
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static inline void uaccess_disable_privileged(void)
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@ -2164,7 +2164,6 @@ static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int sco
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return cpu_supports_bbml2_noabort();
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}
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#ifdef CONFIG_ARM64_PAN
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static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
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{
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/*
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@ -2176,7 +2175,6 @@ static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
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set_pstate_pan(1);
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}
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#endif /* CONFIG_ARM64_PAN */
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#ifdef CONFIG_ARM64_RAS_EXTN
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static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
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@ -2541,7 +2539,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.matches = has_cpuid_feature,
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ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF)
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},
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#ifdef CONFIG_ARM64_PAN
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{
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.desc = "Privileged Access Never",
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.capability = ARM64_HAS_PAN,
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@ -2550,7 +2547,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.cpu_enable = cpu_enable_pan,
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ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP)
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},
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#endif /* CONFIG_ARM64_PAN */
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#ifdef CONFIG_ARM64_EPAN
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{
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.desc = "Enhanced Privileged Access Never",
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@ -126,7 +126,7 @@ SYM_INNER_LABEL(__guest_exit, SYM_L_GLOBAL)
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add x1, x1, #VCPU_CONTEXT
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ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
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ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN)
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// Store the guest regs x2 and x3
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stp x2, x3, [x1, #CPU_XREG_OFFSET(2)]
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