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i2c: wmt: rename something
1. The I2C IP for both wmt and zhaoxin originates from VIA. Rename common registers, functions, and variable names to follow the VIAI2C_ and viai2c_ naming conventions for consistency and clarity. 2. rename i2c_dev to i2c, to shorten the length of a line. 3. rename wait_result to time_left, make it better to reflect the meaning of the value returned by wait_for_completion_timeout(). 4. remove TCR_MASTER_WRITE, its value is 0. Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Hans Hu <hanshu-oc@zhaoxin.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Hans Hu
Andi Shyti
parent
5acd48fa72
commit
013fa161a4
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@ -2,14 +2,14 @@
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#include <linux/of_irq.h>
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#include "i2c-viai2c-common.h"
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int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
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int viai2c_wait_bus_not_busy(struct viai2c *i2c)
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{
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unsigned long timeout;
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timeout = jiffies + WMT_I2C_TIMEOUT;
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while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
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timeout = jiffies + VIAI2C_TIMEOUT;
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while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) {
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if (time_after(jiffies, timeout)) {
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dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
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dev_warn(i2c->dev, "timeout waiting for bus ready\n");
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return -EBUSY;
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}
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msleep(20);
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@ -18,28 +18,28 @@ int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
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return 0;
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}
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int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
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int viai2c_check_status(struct viai2c *i2c)
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{
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int ret = 0;
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unsigned long wait_result;
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unsigned long time_left;
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wait_result = wait_for_completion_timeout(&i2c_dev->complete,
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msecs_to_jiffies(500));
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if (!wait_result)
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time_left = wait_for_completion_timeout(&i2c->complete,
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msecs_to_jiffies(500));
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if (!time_left)
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return -ETIMEDOUT;
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if (i2c_dev->cmd_status & ISR_NACK_ADDR)
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if (i2c->cmd_status & VIAI2C_ISR_NACK_ADDR)
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ret = -EIO;
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if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
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if (i2c->cmd_status & VIAI2C_ISR_SCL_TIMEOUT)
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ret = -ETIMEDOUT;
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return ret;
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}
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static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg, int last)
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static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last)
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{
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u16 val, tcr_val = i2c_dev->tcr;
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u16 val, tcr_val = i2c->tcr;
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int ret;
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int xfer_len = 0;
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@ -49,173 +49,172 @@ static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg, int
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* start at -1 and break out early from the loop
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*/
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xfer_len = -1;
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writew(0, i2c_dev->base + REG_CDR);
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writew(0, i2c->base + VIAI2C_REG_CDR);
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} else {
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writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
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writew(pmsg->buf[0] & 0xFF, i2c->base + VIAI2C_REG_CDR);
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}
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if (!(pmsg->flags & I2C_M_NOSTART)) {
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val = readw(i2c_dev->base + REG_CR);
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val &= ~CR_TX_END;
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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val = readw(i2c->base + VIAI2C_REG_CR);
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val &= ~VIAI2C_CR_TX_END;
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val |= VIAI2C_CR_CPU_RDY;
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writew(val, i2c->base + VIAI2C_REG_CR);
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}
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reinit_completion(&i2c_dev->complete);
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reinit_completion(&i2c->complete);
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tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
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tcr_val |= pmsg->addr & VIAI2C_TCR_ADDR_MASK;
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writew(tcr_val, i2c_dev->base + REG_TCR);
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writew(tcr_val, i2c->base + VIAI2C_REG_TCR);
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if (pmsg->flags & I2C_M_NOSTART) {
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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val = readw(i2c->base + VIAI2C_REG_CR);
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val |= VIAI2C_CR_CPU_RDY;
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writew(val, i2c->base + VIAI2C_REG_CR);
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}
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while (xfer_len < pmsg->len) {
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ret = wmt_check_status(i2c_dev);
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ret = viai2c_check_status(i2c);
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if (ret)
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return ret;
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xfer_len++;
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val = readw(i2c_dev->base + REG_CSR);
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if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
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dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
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val = readw(i2c->base + VIAI2C_REG_CSR);
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if (val & VIAI2C_CSR_RCV_NOT_ACK) {
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dev_dbg(i2c->dev, "write RCV NACK error\n");
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return -EIO;
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}
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if (pmsg->len == 0) {
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val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
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writew(val, i2c_dev->base + REG_CR);
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val = VIAI2C_CR_TX_END | VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE;
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writew(val, i2c->base + VIAI2C_REG_CR);
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break;
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}
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if (xfer_len == pmsg->len) {
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if (last != 1)
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writew(CR_ENABLE, i2c_dev->base + REG_CR);
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writew(VIAI2C_CR_ENABLE, i2c->base + VIAI2C_REG_CR);
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} else {
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writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
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REG_CDR);
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writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
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writew(pmsg->buf[xfer_len] & 0xFF, i2c->base + VIAI2C_REG_CDR);
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writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, i2c->base + VIAI2C_REG_CR);
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}
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}
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return 0;
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}
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static int wmt_i2c_read(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg)
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static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg)
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{
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u16 val, tcr_val = i2c_dev->tcr;
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u16 val, tcr_val = i2c->tcr;
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int ret;
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u32 xfer_len = 0;
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val = readw(i2c_dev->base + REG_CR);
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val &= ~(CR_TX_END | CR_TX_NEXT_NO_ACK);
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val = readw(i2c->base + VIAI2C_REG_CR);
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val &= ~(VIAI2C_CR_TX_END | VIAI2C_CR_RX_END);
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if (!(pmsg->flags & I2C_M_NOSTART))
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val |= CR_CPU_RDY;
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val |= VIAI2C_CR_CPU_RDY;
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if (pmsg->len == 1)
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val |= CR_TX_NEXT_NO_ACK;
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val |= VIAI2C_CR_RX_END;
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writew(val, i2c_dev->base + REG_CR);
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writew(val, i2c->base + VIAI2C_REG_CR);
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reinit_completion(&i2c_dev->complete);
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reinit_completion(&i2c->complete);
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tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
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tcr_val |= VIAI2C_TCR_READ | (pmsg->addr & VIAI2C_TCR_ADDR_MASK);
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writew(tcr_val, i2c_dev->base + REG_TCR);
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writew(tcr_val, i2c->base + VIAI2C_REG_TCR);
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if (pmsg->flags & I2C_M_NOSTART) {
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val = readw(i2c_dev->base + REG_CR);
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val |= CR_CPU_RDY;
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writew(val, i2c_dev->base + REG_CR);
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val = readw(i2c->base + VIAI2C_REG_CR);
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val |= VIAI2C_CR_CPU_RDY;
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writew(val, i2c->base + VIAI2C_REG_CR);
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}
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while (xfer_len < pmsg->len) {
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ret = wmt_check_status(i2c_dev);
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ret = viai2c_check_status(i2c);
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if (ret)
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return ret;
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pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
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pmsg->buf[xfer_len] = readw(i2c->base + VIAI2C_REG_CDR) >> 8;
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xfer_len++;
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val = readw(i2c_dev->base + REG_CR) | CR_CPU_RDY;
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val = readw(i2c->base + VIAI2C_REG_CR) | VIAI2C_CR_CPU_RDY;
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if (xfer_len == pmsg->len - 1)
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val |= CR_TX_NEXT_NO_ACK;
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writew(val, i2c_dev->base + REG_CR);
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val |= VIAI2C_CR_RX_END;
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writew(val, i2c->base + VIAI2C_REG_CR);
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}
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return 0;
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}
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int wmt_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct i2c_msg *pmsg;
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int i;
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int ret = 0;
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struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
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struct viai2c *i2c = i2c_get_adapdata(adap);
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for (i = 0; ret >= 0 && i < num; i++) {
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pmsg = &msgs[i];
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if (!(pmsg->flags & I2C_M_NOSTART)) {
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ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
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ret = viai2c_wait_bus_not_busy(i2c);
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if (ret < 0)
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return ret;
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}
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if (pmsg->flags & I2C_M_RD)
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ret = wmt_i2c_read(i2c_dev, pmsg);
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ret = viai2c_read(i2c, pmsg);
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else
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ret = wmt_i2c_write(i2c_dev, pmsg, (i + 1) == num);
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ret = viai2c_write(i2c, pmsg, (i + 1) == num);
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}
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return (ret < 0) ? ret : i;
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}
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static irqreturn_t wmt_i2c_isr(int irq, void *data)
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static irqreturn_t viai2c_isr(int irq, void *data)
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{
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struct wmt_i2c_dev *i2c_dev = data;
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struct viai2c *i2c = data;
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/* save the status and write-clear it */
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i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
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writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
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i2c->cmd_status = readw(i2c->base + VIAI2C_REG_ISR);
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writew(i2c->cmd_status, i2c->base + VIAI2C_REG_ISR);
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complete(&i2c_dev->complete);
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complete(&i2c->complete);
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return IRQ_HANDLED;
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}
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int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c_dev **pi2c_dev)
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int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c)
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{
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int err;
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struct wmt_i2c_dev *i2c_dev;
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struct viai2c *i2c;
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struct device_node *np = pdev->dev.of_node;
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i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
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if (!i2c_dev)
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i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(i2c_dev->base))
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return PTR_ERR(i2c_dev->base);
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i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(i2c->base))
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return PTR_ERR(i2c->base);
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i2c_dev->irq = irq_of_parse_and_map(np, 0);
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if (!i2c_dev->irq)
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i2c->irq = irq_of_parse_and_map(np, 0);
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if (!i2c->irq)
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return -EINVAL;
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err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr,
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0, pdev->name, i2c_dev);
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err = devm_request_irq(&pdev->dev, i2c->irq, viai2c_isr,
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0, pdev->name, i2c);
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if (err)
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return dev_err_probe(&pdev->dev, err,
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"failed to request irq %i\n", i2c_dev->irq);
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"failed to request irq %i\n", i2c->irq);
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i2c_dev->dev = &pdev->dev;
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init_completion(&i2c_dev->complete);
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platform_set_drvdata(pdev, i2c_dev);
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i2c->dev = &pdev->dev;
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init_completion(&i2c->complete);
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platform_set_drvdata(pdev, i2c);
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*pi2c_dev = i2c_dev;
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*pi2c = i2c;
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return 0;
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}
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@ -11,48 +11,46 @@
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#define REG_CR 0x00
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#define REG_TCR 0x02
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#define REG_CSR 0x04
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#define REG_ISR 0x06
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#define REG_IMR 0x08
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#define REG_CDR 0x0A
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#define REG_TR 0x0C
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#define REG_MCR 0x0E
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/* REG_CR Bit fields */
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#define CR_TX_NEXT_ACK 0x0000
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#define CR_ENABLE 0x0001
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#define CR_TX_NEXT_NO_ACK 0x0002
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#define CR_TX_END 0x0004
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#define CR_CPU_RDY 0x0008
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#define SLAV_MODE_SEL 0x8000
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#define VIAI2C_REG_CR 0x00
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#define VIAI2C_CR_ENABLE BIT(0)
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#define VIAI2C_CR_RX_END BIT(1)
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#define VIAI2C_CR_TX_END BIT(2)
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#define VIAI2C_CR_CPU_RDY BIT(3)
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#define VIAI2C_CR_END_MASK GENMASK(2, 1)
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/* REG_TCR Bit fields */
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#define TCR_STANDARD_MODE 0x0000
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#define TCR_MASTER_WRITE 0x0000
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#define TCR_HS_MODE 0x2000
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#define TCR_MASTER_READ 0x4000
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#define TCR_FAST_MODE 0x8000
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#define TCR_SLAVE_ADDR_MASK 0x007F
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/* REG_ISR Bit fields */
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#define ISR_NACK_ADDR 0x0001
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#define ISR_BYTE_END 0x0002
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#define ISR_SCL_TIMEOUT 0x0004
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#define ISR_WRITE_ALL 0x0007
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/* REG_IMR Bit fields */
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#define IMR_ENABLE_ALL 0x0007
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#define VIAI2C_REG_TCR 0x02
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#define VIAI2C_TCR_HS_MODE BIT(13)
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#define VIAI2C_TCR_READ BIT(14)
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#define VIAI2C_TCR_FAST BIT(15)
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#define VIAI2C_TCR_ADDR_MASK GENMASK(6, 0)
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/* REG_CSR Bit fields */
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#define CSR_RCV_NOT_ACK 0x0001
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#define CSR_RCV_ACK_MASK 0x0001
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#define CSR_READY_MASK 0x0002
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#define VIAI2C_REG_CSR 0x04
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#define VIAI2C_CSR_RCV_NOT_ACK BIT(0)
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#define VIAI2C_CSR_RCV_ACK_MASK BIT(0)
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#define VIAI2C_CSR_READY_MASK BIT(1)
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#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
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/* REG_ISR Bit fields */
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#define VIAI2C_REG_ISR 0x06
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#define VIAI2C_ISR_NACK_ADDR BIT(0)
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#define VIAI2C_ISR_BYTE_END BIT(1)
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#define VIAI2C_ISR_SCL_TIMEOUT BIT(2)
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#define VIAI2C_ISR_MASK_ALL GENMASK(2, 0)
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struct wmt_i2c_dev {
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/* REG_IMR Bit fields */
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#define VIAI2C_REG_IMR 0x08
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#define VIAI2C_IMR_BYTE BIT(1)
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#define VIAI2C_IMR_ENABLE_ALL GENMASK(2, 0)
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#define VIAI2C_REG_CDR 0x0A
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#define VIAI2C_REG_TR 0x0C
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#define VIAI2C_REG_MCR 0x0E
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#define VIAI2C_TIMEOUT (msecs_to_jiffies(1000))
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||||
struct viai2c {
|
||||
struct i2c_adapter adapter;
|
||||
struct completion complete;
|
||||
struct device *dev;
|
||||
|
|
@ -63,9 +61,9 @@ struct wmt_i2c_dev {
|
|||
u16 cmd_status;
|
||||
};
|
||||
|
||||
int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev);
|
||||
int wmt_check_status(struct wmt_i2c_dev *i2c_dev);
|
||||
int wmt_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num);
|
||||
int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c_dev **pi2c_dev);
|
||||
int viai2c_wait_bus_not_busy(struct viai2c *i2c);
|
||||
int viai2c_check_status(struct viai2c *i2c);
|
||||
int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num);
|
||||
int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -35,39 +35,39 @@ static u32 wmt_i2c_func(struct i2c_adapter *adap)
|
|||
}
|
||||
|
||||
static const struct i2c_algorithm wmt_i2c_algo = {
|
||||
.master_xfer = wmt_i2c_xfer,
|
||||
.master_xfer = viai2c_xfer,
|
||||
.functionality = wmt_i2c_func,
|
||||
};
|
||||
|
||||
static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
|
||||
static int wmt_i2c_reset_hardware(struct viai2c *i2c)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = clk_prepare_enable(i2c_dev->clk);
|
||||
err = clk_prepare_enable(i2c->clk);
|
||||
if (err) {
|
||||
dev_err(i2c_dev->dev, "failed to enable clock\n");
|
||||
dev_err(i2c->dev, "failed to enable clock\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_set_rate(i2c_dev->clk, 20000000);
|
||||
err = clk_set_rate(i2c->clk, 20000000);
|
||||
if (err) {
|
||||
dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
|
||||
clk_disable_unprepare(i2c_dev->clk);
|
||||
dev_err(i2c->dev, "failed to set clock = 20Mhz\n");
|
||||
clk_disable_unprepare(i2c->clk);
|
||||
return err;
|
||||
}
|
||||
|
||||
writew(0, i2c_dev->base + REG_CR);
|
||||
writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
|
||||
writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
|
||||
writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
|
||||
writew(CR_ENABLE, i2c_dev->base + REG_CR);
|
||||
readw(i2c_dev->base + REG_CSR); /* read clear */
|
||||
writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
|
||||
writew(0, i2c->base + VIAI2C_REG_CR);
|
||||
writew(MCR_APB_166M, i2c->base + VIAI2C_REG_MCR);
|
||||
writew(VIAI2C_ISR_MASK_ALL, i2c->base + VIAI2C_REG_ISR);
|
||||
writew(VIAI2C_IMR_ENABLE_ALL, i2c->base + VIAI2C_REG_IMR);
|
||||
writew(VIAI2C_CR_ENABLE, i2c->base + VIAI2C_REG_CR);
|
||||
readw(i2c->base + VIAI2C_REG_CSR); /* read clear */
|
||||
writew(VIAI2C_ISR_MASK_ALL, i2c->base + VIAI2C_REG_ISR);
|
||||
|
||||
if (i2c_dev->tcr == TCR_FAST_MODE)
|
||||
writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
|
||||
if (i2c->tcr == VIAI2C_TCR_FAST)
|
||||
writew(SCL_TIMEOUT(128) | TR_HS, i2c->base + VIAI2C_REG_TR);
|
||||
else
|
||||
writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
|
||||
writew(SCL_TIMEOUT(128) | TR_STD, i2c->base + VIAI2C_REG_TR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -75,34 +75,34 @@ static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
|
|||
static int wmt_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct wmt_i2c_dev *i2c_dev;
|
||||
struct viai2c *i2c;
|
||||
struct i2c_adapter *adap;
|
||||
int err;
|
||||
u32 clk_rate;
|
||||
|
||||
err = wmt_i2c_init(pdev, &i2c_dev);
|
||||
err = viai2c_init(pdev, &i2c);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
i2c_dev->clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(i2c_dev->clk)) {
|
||||
i2c->clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(i2c->clk)) {
|
||||
dev_err(&pdev->dev, "unable to request clock\n");
|
||||
return PTR_ERR(i2c_dev->clk);
|
||||
return PTR_ERR(i2c->clk);
|
||||
}
|
||||
|
||||
err = of_property_read_u32(np, "clock-frequency", &clk_rate);
|
||||
if (!err && clk_rate == I2C_MAX_FAST_MODE_FREQ)
|
||||
i2c_dev->tcr = TCR_FAST_MODE;
|
||||
i2c->tcr = VIAI2C_TCR_FAST;
|
||||
|
||||
adap = &i2c_dev->adapter;
|
||||
i2c_set_adapdata(adap, i2c_dev);
|
||||
adap = &i2c->adapter;
|
||||
i2c_set_adapdata(adap, i2c);
|
||||
strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->algo = &wmt_i2c_algo;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
adap->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
err = wmt_i2c_reset_hardware(i2c_dev);
|
||||
err = wmt_i2c_reset_hardware(i2c);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "error initializing hardware\n");
|
||||
return err;
|
||||
|
|
@ -111,19 +111,19 @@ static int wmt_i2c_probe(struct platform_device *pdev)
|
|||
err = i2c_add_adapter(adap);
|
||||
if (err)
|
||||
/* wmt_i2c_reset_hardware() enables i2c_dev->clk */
|
||||
clk_disable_unprepare(i2c_dev->clk);
|
||||
clk_disable_unprepare(i2c->clk);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void wmt_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
|
||||
struct viai2c *i2c = platform_get_drvdata(pdev);
|
||||
|
||||
/* Disable interrupts, clock and delete adapter */
|
||||
writew(0, i2c_dev->base + REG_IMR);
|
||||
clk_disable_unprepare(i2c_dev->clk);
|
||||
i2c_del_adapter(&i2c_dev->adapter);
|
||||
writew(0, i2c->base + VIAI2C_REG_IMR);
|
||||
clk_disable_unprepare(i2c->clk);
|
||||
i2c_del_adapter(&i2c->adapter);
|
||||
}
|
||||
|
||||
static const struct of_device_id wmt_i2c_dt_ids[] = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user