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Merge branches 'fixes' and 'misc' into for-next

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Russell King (Oracle) 2026-10-14 17:27:00 +01:00 committed by Russell King
commit 01330dac0f
5 changed files with 33 additions and 26 deletions
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8
arch/arm/boot/compressed/Makefile
View File

@ -41,14 +41,6 @@ ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y)
OBJS += head-sharpsl.o
endif
ifeq ($(CONFIG_CPU_ENDIAN_BE32),y)
ifeq ($(CONFIG_CPU_CP15),y)
OBJS += big-endian.o
else
# The endian should be set by h/w design.
endif
endif
#
# We now have a PIC decompressor implementation. Decompressors running
# from RAM should not define ZTEXTADDR. Decompressors running directly

14
arch/arm/boot/compressed/big-endian.S
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/boot/compressed/big-endian.S
*
* Switch CPU into big endian mode.
* Author: Nicolas Pitre
*/
.section ".start", "ax"
mrc p15, 0, r0, c1, c0, 0 @ read control reg
orr r0, r0, #(1 << 7) @ enable big endian mode
mcr p15, 0, r0, c1, c0, 0 @ write control reg

18
arch/arm/boot/compressed/head-xscale.S
View File

@ -7,6 +7,7 @@
*/
#include <linux/linkage.h>
#include <asm/cp15.h>
.section ".start", "ax"
@ -14,6 +15,23 @@ __XScale_start:
@ Preserve r8/r7 i.e. kernel entry values
@ set correct endianness for ixp4xx regardless of bootloader
mrc p15, 0, r0, c1, c0, 0
#ifdef CONFIG_CPU_BIG_ENDIAN
orr r0, r0, #CR_B @ enable big endian mode
#else
bic r0, r0, #CR_B
#endif
mcr p15, 0, r0, c1, c0, 0
0: mrc p15, 0, r0, c1, c0, 0
tst r0, #0x80
#ifdef CONFIG_CPU_BIG_ENDIAN
beq 0b
#else
bne 0b
#endif
sub pc, pc, #4 @ flush instruction pipeline
@ Data cache might be active.
@ Be sure to flush kernel binary out of the cache,
@ whatever state it is, before it is turned off.

4
arch/arm/lib/backtrace-clang.S
View File

@ -107,8 +107,10 @@ ENDPROC(c_backtrace)
/*
* Switches the current frame to be the frame for dump_stack.
* (Only in case of current task using current registers)
*/
add frame, sp, #24 @ switch to false frame
cmp frame, fp
addeq frame, sp, #24 @ switch to false frame
for_each_frame: tst frame, mask @ Check for address exceptions
bne no_frame

15
arch/arm/mm/context.c
View File

@ -238,7 +238,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
{
unsigned long flags;
unsigned int cpu = smp_processor_id();
u64 asid;
u64 asid, old_active_asid;
check_vmalloc_seq(mm);
@ -250,8 +250,17 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
cpu_set_reserved_ttbr0();
asid = atomic64_read(&mm->context.id);
if (!((asid ^ atomic64_read(&asid_generation)) >> ASID_BITS)
&& atomic64_xchg(&per_cpu(active_asids, cpu), asid))
/*
* If our active_asids is zero, we are racing with an ASID roll-over
* on a different CPU, so skip the update (using cmpxchg if non-zero)
* and take the slow path.
*/
old_active_asid = atomic64_read(&per_cpu(active_asids, cpu));
if (old_active_asid &&
!((asid ^ atomic64_read(&asid_generation)) >> ASID_BITS) &&
atomic64_cmpxchg(&per_cpu(active_asids, cpu),
old_active_asid, asid))
goto switch_mm_fastpath;
raw_spin_lock_irqsave(&cpu_asid_lock, flags);