github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-27 16:44:58 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amd/display: Refactor input mode programming for DIG FIFO

Browse Source 
[WHY]
Input mode for the DIG FIFO should be programmed as part of stream
encoder setup.

[HOW]
Pre-calculate the pixels per cycle as part of the pixel clock params,
and program as part of stream encoder setup.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone 2024-04-15 13:13:56 -04:00 committed by Alex Deucher
parent 4482b4f6c2
commit 0127f0445f
19 changed files with 103 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
View File

@ -228,7 +228,27 @@ static void enc401_stream_encoder_hdmi_set_stream_attribute(
REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
}
static void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
// The naming of this field is confusing, what it means is the output mode of otg, which
// is the input mode of the dig
switch (pix_per_container) {
case 2:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1);
break;
case 4:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2);
break;
case 8:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3);
break;
default:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0);
break;
}
}
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
{
@ -239,68 +259,28 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
return two_pix;
}
static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing)
{
/* math borrowed from function of same name in inc/resource
* checks if h_timing is divisible by 2
*/
bool divisible = false;
uint16_t h_blank_start = 0;
uint16_t h_blank_end = 0;
if (timing) {
h_blank_start = timing->h_total - timing->h_front_porch;
h_blank_end = h_blank_start - timing->h_addressable;
/* HTOTAL, Hblank start/end, and Hsync start/end all must be
* divisible by 2 in order for the horizontal timing params
* to be considered divisible by 2. Hsync start is always 0.
*/
divisible = (timing->h_total % 2 == 0) &&
(h_blank_start % 2 == 0) &&
(h_blank_end % 2 == 0) &&
(timing->h_sync_width % 2 == 0);
}
return divisible;
}
static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing)
{
/* should be functionally the same as dcn32_is_dp_dig_pixel_rate_div_policy for DP encoders*/
return is_h_timing_divisible_by_2(timing) &&
dc->debug.enable_dp_dig_pixel_rate_div_policy;
}
static void enc401_stream_encoder_dp_unblank(
struct dc_link *link,
struct stream_encoder *enc,
const struct encoder_unblank_param *param)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
struct dc *dc = enc->ctx->dc;
if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
uint32_t n_vid = 0x8000;
uint32_t m_vid;
uint32_t n_multiply = 0;
// TODO: Fix defined but not used
//uint32_t pix_per_cycle = 0;
uint32_t pix_per_container = 1;
uint64_t m_vid_l = n_vid;
/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1
|| is_dp_dig_pixel_rate_div_policy(dc, &param->timing)) {
/*this logic should be the same in get_pixel_clock_parameters() */
n_multiply = 1;
// TODO: Fix defined but not used
//pix_per_cycle = 1;
/* YCbCr 4:2:0 or YCbCr4:2:2 simple + DSC: Computed VID_M will be 2X the input rate */
if (is_two_pixels_per_containter(&param->timing)) {
pix_per_container = 2;
}
/* M / N = Fstream / Flink
* m_vid / n_vid = pixel rate / link rate
*/
m_vid_l *= param->timing.pix_clk_100hz / 10;
m_vid_l *= param->timing.pix_clk_100hz / pix_per_container / 10;
m_vid_l = div_u64(m_vid_l,
param->link_settings.link_rate
* LINK_RATE_REF_FREQ_IN_KHZ);
@ -319,9 +299,23 @@ static void enc401_stream_encoder_dp_unblank(
REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
REG_UPDATE_2(DP_VID_TIMING,
DP_VID_M_N_GEN_EN, 1,
DP_VID_N_INTERVAL, n_multiply);
/* reduce jitter based on read rate */
switch (param->pix_per_cycle) {
case 2:
REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x1);
break;
case 4:
REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x2);
break;
case 8:
REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x3);
break;
default:
REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x0);
break;
}
REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
}
/* make sure stream is disabled before resetting steer fifo */
@ -413,27 +407,6 @@ static void enc401_read_state(struct stream_encoder *enc, struct enc_state *s)
}
}
static void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
// The naming of this field is confusing, what it means is the output mode of otg, which
// is the input mode of the dig
switch (pix_per_container) {
case 2:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1);
break;
case 4:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2);
break;
case 8:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3);
break;
default:
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0);
break;
}
}
static void enc401_stream_encoder_enable(
struct stream_encoder *enc,
enum signal_type signal,

3
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@ -2959,9 +2959,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
early_control = lane_count;
tg->funcs->set_early_control(tg, early_control);
if (dc->hwseq->funcs.set_pixels_per_cycle)
dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
}
void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

17
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
View File

@ -332,23 +332,6 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
return odm_combine_factor;
}
void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
{
uint32_t pix_per_cycle = 1;
uint32_t odm_combine_factor = 1;
if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
return;
odm_combine_factor = get_odm_config(pipe_ctx, NULL);
if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing) || odm_combine_factor > 1)
pix_per_cycle = 2;
if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
pix_per_cycle);
}
void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
{
unsigned int i;

2
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
View File

@ -39,8 +39,6 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);

1
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
View File

@ -152,7 +152,6 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {
.set_shaper_3dlut = dcn20_set_shaper_3dlut,
.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
.calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,
.set_pixels_per_cycle = dcn314_set_pixels_per_cycle,
.resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
};

18
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
View File

@ -1173,24 +1173,6 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign
return odm_combine_factor;
}
void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
{
uint32_t pix_per_cycle = 1;
uint32_t odm_combine_factor = 1;
if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
return;
odm_combine_factor = get_odm_config(pipe_ctx, NULL);
if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing) || odm_combine_factor > 1
|| dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
pix_per_cycle = 2;
if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
pix_per_cycle);
}
void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
{
unsigned int i;

2
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
View File

@ -73,8 +73,6 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);
void dcn32_subvp_pipe_control_lock(struct dc *dc,

1
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
View File

@ -158,7 +158,6 @@ static const struct hwseq_private_funcs dcn32_private_funcs = {
.update_force_pstate = dcn32_update_force_pstate,
.update_mall_sel = dcn32_update_mall_sel,
.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
.resync_fifo_dccg_dio = dcn32_resync_fifo_dccg_dio,
.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
.apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,

1
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
View File

@ -159,7 +159,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
.set_mcm_luts = dcn32_set_mcm_luts,
.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
.resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
.dsc_pg_control = dcn35_dsc_pg_control,

1
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
View File

@ -158,7 +158,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
.set_mcm_luts = dcn32_set_mcm_luts,
.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
.dsc_pg_control = dcn35_dsc_pg_control,
.dsc_pg_status = dcn32_dsc_pg_status,

30
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@ -978,9 +978,6 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)
dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
tg->funcs->set_early_control(tg, early_control);
if (dc->hwseq->funcs.set_pixels_per_cycle)
dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);
}
void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
@ -1545,3 +1542,30 @@ void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool en
dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_required);
}
void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings)
{
struct encoder_unblank_param params = {0};
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
struct dce_hwseq *hws = link->dc->hwseq;
/* calculate parameters for unblank */
params.opp_cnt = resource_get_odm_slice_count(pipe_ctx);
params.timing = pipe_ctx->stream->timing;
params.link_settings.link_rate = link_settings->link_rate;
params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;
if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
pipe_ctx->stream_res.hpo_dp_stream_enc,
pipe_ctx->stream_res.tg->inst);
} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
}
if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
hws->funcs.edp_backlight_control(link, true);
}

1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
View File

@ -72,5 +72,6 @@ void dcn401_fams2_global_control_lock(struct dc *dc,
bool lock);
void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);
void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params);
void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);
#endif /* __DC_HWSS_DCN401_H__ */

4
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
View File

@ -31,7 +31,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
.enable_stream = dcn401_enable_stream,
.disable_stream = dce110_disable_stream,
.unblank_stream = dcn32_unblank_stream,
.unblank_stream = dcn401_unblank_stream,
.blank_stream = dce110_blank_stream,
.enable_audio_stream = dce110_enable_audio_stream,
.disable_audio_stream = dce110_disable_audio_stream,
@ -137,8 +137,6 @@ static const struct hwseq_private_funcs dcn401_private_funcs = {
.update_mall_sel = dcn32_update_mall_sel,
.setup_hpo_hw_control = dcn401_setup_hpo_hw_control,
.calculate_dccg_k1_k2_values = NULL,
.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
.apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
.reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe,
.populate_mcm_luts = dcn401_populate_mcm_luts,

1
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
View File

@ -169,7 +169,6 @@ struct hwseq_private_funcs {
unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div,
unsigned int *k2_div);
void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);
void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,
struct dc_state *context);
enum dc_status (*apply_single_controller_ctx_to_hw)(

1
drivers/gpu/drm/amd/display/dc/inc/clock_source.h
View File

@ -96,6 +96,7 @@ struct pixel_clk_params {
/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
enum dc_pixel_encoding pixel_encoding;
struct pixel_clk_flags flags;
uint32_t dio_se_pix_per_cycle;
};
/**

1
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View File

@ -99,6 +99,7 @@ struct encoder_unblank_param {
struct dc_link_settings link_settings;
struct dc_crtc_timing timing;
int opp_cnt;
uint32_t pix_per_cycle;
};
struct encoder_set_dp_phy_pattern_param {

3
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
View File

@ -49,6 +49,9 @@ void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
if (stream_enc->funcs->map_stream_to_link)
stream_enc->funcs->map_stream_to_link(stream_enc,
stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);
if (stream_enc->funcs->set_input_mode)
stream_enc->funcs->set_input_mode(stream_enc,
pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle);
if (stream_enc->funcs->enable_fifo)
stream_enc->funcs->enable_fifo(stream_enc);
}

9
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
View File

@ -1261,6 +1261,15 @@ static void get_pixel_clock_parameters(
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
pixel_clk_params->requested_pix_clk_100hz *= 2;
if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&
pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||
(hws->funcs.is_dp_dig_pixel_rate_div_policy &&
hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||
opp_cnt > 1) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else {
pixel_clk_params->dio_se_pix_per_cycle = 1;
}
}
static void build_clamping_params(struct dc_stream_state *stream)

18
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
View File

@ -1645,7 +1645,6 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
pixel_clk_params->color_depth = COLOR_DEPTH_888;
/* TODO: Do we still need this? */
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
pixel_clk_params->requested_pix_clk_100hz *= 2;
if (dc_is_tmds_signal(stream->signal) &&
@ -1656,6 +1655,23 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
pipe_ctx->clock_source,
&pipe_ctx->stream_res.pix_clk_params,
&pipe_ctx->pll_settings);
pixel_clk_params->dio_se_pix_per_cycle = 1;
if (dc_is_tmds_signal(stream->signal) &&
stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else if (dc_is_dp_signal(stream->signal)) {
/* round up to nearest power of 2, or max at 8 pixels per cycle */
if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
pixel_clk_params->dio_se_pix_per_cycle = 8;
} else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
pixel_clk_params->dio_se_pix_per_cycle = 4;
} else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else {
pixel_clk_params->dio_se_pix_per_cycle = 1;
}
}
}
static struct resource_funcs dcn401_res_pool_funcs = {