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arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes

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With the exception of cmu_top, each CMU has a corresponding sysreg bank
that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers.
The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of
bus components and MEMCLK gates the sram clock.

Now the clock driver supports automatic clock mode, provide the
samsung,sysreg property so the driver can enable dynamic root clock
gating of bus components and gate sram clock.

Note without the property specified the driver simply falls back to
previous behaviour of not configuring these registers so it is not an ABI
break.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20251222-automatic-clocks-v7-2-fec86fa89874@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Peter Griffin 2025-12-22 10:22:13 +00:00 committed by Krzysztof Kozlowski
parent abc6930a31
commit 01272f05aa
1 changed files with 6 additions and 0 deletions
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6
arch/arm64/boot/dts/exynos/google/gs101.dtsi
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@ -578,6 +578,7 @@ cmu_misc: clock-controller@10010000 {
clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
<&cmu_top CLK_DOUT_CMU_MISC_SSS>;
clock-names = "bus", "sss";
samsung,sysreg = <&sysreg_misc>;
};
sysreg_misc: syscon@10030000 {
@ -671,6 +672,7 @@ cmu_peric0: clock-controller@10800000 {
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
clock-names = "oscclk", "bus", "ip";
samsung,sysreg = <&sysreg_peric0>;
};
sysreg_peric0: syscon@10820000 {
@ -1217,6 +1219,7 @@ cmu_peric1: clock-controller@10c00000 {
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
clock-names = "oscclk", "bus", "ip";
samsung,sysreg = <&sysreg_peric1>;
};
sysreg_peric1: syscon@10c20000 {
@ -1575,6 +1578,7 @@ cmu_hsi0: clock-controller@11000000 {
<&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
clock-names = "oscclk", "bus", "dpgtc", "usb31drd",
"usbdpdbg";
samsung,sysreg = <&sysreg_hsi0>;
};
sysreg_hsi0: syscon@11020000 {
@ -1646,6 +1650,7 @@ cmu_hsi2: clock-controller@14400000 {
<&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
<&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
samsung,sysreg = <&sysreg_hsi2>;
};
sysreg_hsi2: syscon@14420000 {
@ -1706,6 +1711,7 @@ cmu_apm: clock-controller@17400000 {
clocks = <&ext_24_5m>;
clock-names = "oscclk";
samsung,sysreg = <&sysreg_apm>;
};
sysreg_apm: syscon@17420000 {