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drm/xe/pat: Define PAT tables as static

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The tables are only used within this file; there's no reason for them
not to be static.

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230327175824.2967914-1-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-03-27 10:58:24 -07:00 committed by Rodrigo Vivi
parent e7dc1341f0
commit 011d8fa362
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/xe/xe_pat.c
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@ -32,7 +32,7 @@
#define TGL_PAT_WC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 1)
#define TGL_PAT_UC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 0)
const u32 tgl_pat_table[] = {
static const u32 tgl_pat_table[] = {
[0] = TGL_PAT_WB,
[1] = TGL_PAT_WC,
[2] = TGL_PAT_WT,
@ -43,7 +43,7 @@ const u32 tgl_pat_table[] = {
[7] = TGL_PAT_WB,
};
const u32 pvc_pat_table[] = {
static const u32 pvc_pat_table[] = {
[0] = TGL_PAT_UC,
[1] = TGL_PAT_WC,
[2] = TGL_PAT_WT,
@ -54,7 +54,7 @@ const u32 pvc_pat_table[] = {
[7] = PVC_PAT_CLOS(2) | TGL_PAT_WB,
};
const u32 mtl_pat_table[] = {
static const u32 mtl_pat_table[] = {
[0] = MTL_PAT_0_WB,
[1] = MTL_PAT_1_WT,
[2] = MTL_PAT_3_UC,