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drm/tegra: dp: fix kernel-doc warnings in dp.h

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Use correct kernel-doc format and add missing nested struct entries to
eliminate kernel-doc warnings:

Warning: drivers/gpu/drm/tegra/dp.h:28 Incorrect use of kernel-doc format:
 * tps3_supported:
Warning: drivers/gpu/drm/tegra/dp.h:54 struct member 'tps3_supported'
 not described in 'drm_dp_link_caps'
dp.h:73: warning: Function parameter or struct member 'apply_training'
 not described in 'drm_dp_link_ops'
dp.h:73: warning: Function parameter or struct member 'configure'
 not described in 'drm_dp_link_ops'
dp.h:160: warning: Excess struct member 'cr' description in 'drm_dp_link'

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Acked-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patch.msgid.link/20260427184442.693768-1-rdunlap@infradead.org
This commit is contained in:
Randy Dunlap 2026-04-27 11:44:42 -07:00 committed by Thierry Reding
parent 71d25f668b
commit 011c4b65e3
1 changed files with 5 additions and 7 deletions
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12
drivers/gpu/drm/tegra/dp.h
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@ -26,7 +26,7 @@ struct drm_dp_link_caps {
bool enhanced_framing;
/**
* tps3_supported:
* @tps3_supported:
*
* training pattern sequence 3 supported for equalization
*/
@ -62,12 +62,12 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
*/
struct drm_dp_link_ops {
/**
* @apply_training:
* @apply_training: apply the link training
*/
int (*apply_training)(struct drm_dp_link *link);
/**
* @configure:
* @configure: configure the DP link
*/
int (*configure)(struct drm_dp_link *link);
};
@ -113,6 +113,8 @@ struct drm_dp_link_train {
* @max_lanes: maximum number of lanes supported on the link
* @caps: capabilities supported on the link (see &drm_dp_link_caps)
* @aux_rd_interval: AUX read interval to use for training (in microseconds)
* @aux_rd_interval.cr: clock recovery read interval
* @aux_rd_interval.ce: channel equalization read interval
* @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
* @rate: currently configured link rate
* @lanes: currently configured number of lanes
@ -126,10 +128,6 @@ struct drm_dp_link {
struct drm_dp_link_caps caps;
/**
* @cr: clock recovery read interval
* @ce: channel equalization read interval
*/
struct {
unsigned int cr;
unsigned int ce;