From fc6c8af6d784961b7f19bf0870baa1cdab5f7ad5 Mon Sep 17 00:00:00 2001 From: Jacky Chou Date: Wed, 9 Jul 2025 15:08:06 +0800 Subject: [PATCH 1/3] dt-bindings: net: ftgmac100: Add resets property In Aspeed AST2600 design, the MAC internal delay on MAC register cannot fully reset the RMII interfaces, it may cause the RMII incompletely. Therefore, we need to add resets property to do SoC-level reset line to reset the whole MAC function that includes ftgmac, RGMII and RMII. Signed-off-by: Jacky Chou Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250709070809.2560688-2-jacky_chou@aspeedtech.com Signed-off-by: Jakub Kicinski --- .../bindings/net/faraday,ftgmac100.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 55d6a8379025..d14410018bcf 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FTGMAC100 gigabit ethernet controller -allOf: - - $ref: ethernet-controller.yaml# - maintainers: - Po-Yu Chuang @@ -35,6 +32,9 @@ properties: - description: MAC IP clock - description: RMII RCLK gate for AST2500/2600 + resets: + maxItems: 1 + clock-names: minItems: 1 items: @@ -74,6 +74,21 @@ required: - reg - interrupts +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-mac + then: + properties: + resets: true + else: + properties: + resets: false + unevaluatedProperties: false examples: From 4dc5f7b2c0ccf233d16c5f3090208d70954f1e2a Mon Sep 17 00:00:00 2001 From: Jacky Chou Date: Wed, 9 Jul 2025 15:08:07 +0800 Subject: [PATCH 2/3] dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2 Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to the ast2600-clock binding header. These are required for proper reset control of the MAC1 and MAC2 ethernet controllers on the AST2600 SoC. Signed-off-by: Jacky Chou Acked-by: Conor Dooley Acked-by: Stephen Boyd Link: https://patch.msgid.link/20250709070809.2560688-3-jacky_chou@aspeedtech.com Signed-off-by: Jakub Kicinski --- include/dt-bindings/clock/ast2600-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 7ae96c7bd72f..f60fff261130 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -122,6 +122,8 @@ #define ASPEED_RESET_PCIE_DEV_OEN 20 #define ASPEED_RESET_PCIE_RC_O 19 #define ASPEED_RESET_PCIE_RC_OEN 18 +#define ASPEED_RESET_MAC2 12 +#define ASPEED_RESET_MAC1 11 #define ASPEED_RESET_PCI_DP 5 #define ASPEED_RESET_HACE 4 #define ASPEED_RESET_AHB 1 From af350ee72e9dda474af4697ff59601cb73387b31 Mon Sep 17 00:00:00 2001 From: Jacky Chou Date: Wed, 9 Jul 2025 15:08:09 +0800 Subject: [PATCH 3/3] net: ftgmac100: Add optional reset control for RMII mode on Aspeed SoCs On Aspeed SoCs, the internal MAC reset is insufficient to fully reset the RMII interface; only the SoC-level reset line can properly reset the RMII logic. This patch adds support for an optional "resets" property in the device tree, allowing the driver to assert and deassert the SoC reset line when operating in RMII mode. This ensures the MAC and RMII interface are correctly reset and initialized. Signed-off-by: Jacky Chou Reviewed-by: Andrew Lunn Link: https://patch.msgid.link/20250709070809.2560688-5-jacky_chou@aspeedtech.com Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/faraday/ftgmac100.c | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index a98d5af3f9e3..05b8e3743a79 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -101,6 +102,8 @@ struct ftgmac100 { /* AST2500/AST2600 RMII ref clock gate */ struct clk *rclk; + /* Aspeed reset control */ + struct reset_control *rst; /* Link management */ int cur_speed; @@ -148,6 +151,23 @@ static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) { u32 maccr = 0; + /* Aspeed RMII needs SCU reset to clear status */ + if (priv->is_aspeed && priv->netdev->phydev->interface == PHY_INTERFACE_MODE_RMII) { + int err; + + err = reset_control_assert(priv->rst); + if (err) { + dev_err(priv->dev, "Failed to reset mac (%d)\n", err); + return err; + } + usleep_range(10000, 20000); + err = reset_control_deassert(priv->rst); + if (err) { + dev_err(priv->dev, "Failed to deassert mac reset (%d)\n", err); + return err; + } + } + switch (priv->cur_speed) { case SPEED_10: case 0: /* no link */ @@ -1968,6 +1988,12 @@ static int ftgmac100_probe(struct platform_device *pdev) } + priv->rst = devm_reset_control_get_optional_exclusive(priv->dev, NULL); + if (IS_ERR(priv->rst)) { + err = PTR_ERR(priv->rst); + goto err_phy_connect; + } + if (priv->is_aspeed) { err = ftgmac100_setup_clk(priv); if (err)