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x86/mce: Ensure user polling settings are honored when restarting timer
Users can disable MCA polling by setting the "ignore_ce" parameter or by
setting "check_interval=0". This tells the kernel to *not* start the MCE
timer on a CPU.
If the user did not disable CMCI, then storms can occur. When these
happen, the MCE timer will be started with a fixed interval. After the
storm subsides, the timer's next interval is set to check_interval.
This disregards the user's input through "ignore_ce" and
"check_interval". Furthermore, if "check_interval=0", then the new timer
will run faster than expected.
Create a new helper to check these conditions and use it when a CMCI
storm ends.
[ bp: Massage. ]
Fixes: 7eae17c4ad ("x86/mce: Add per-bank CMCI storm mitigation")
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/20250624-wip-mca-updates-v4-2-236dd74f645f@amd.com
This commit is contained in:
parent
4c113a5b28
commit
00c092de6f
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@ -1740,6 +1740,11 @@ static void mc_poll_banks_default(void)
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void (*mc_poll_banks)(void) = mc_poll_banks_default;
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static bool should_enable_timer(unsigned long iv)
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{
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return !mca_cfg.ignore_ce && iv;
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}
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static void mce_timer_fn(struct timer_list *t)
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{
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struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
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@ -1763,7 +1768,7 @@ static void mce_timer_fn(struct timer_list *t)
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if (mce_get_storm_mode()) {
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__start_timer(t, HZ);
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} else {
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} else if (should_enable_timer(iv)) {
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__this_cpu_write(mce_next_interval, iv);
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__start_timer(t, iv);
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}
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@ -2156,11 +2161,10 @@ static void mce_start_timer(struct timer_list *t)
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{
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unsigned long iv = check_interval * HZ;
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if (mca_cfg.ignore_ce || !iv)
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return;
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this_cpu_write(mce_next_interval, iv);
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__start_timer(t, iv);
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if (should_enable_timer(iv)) {
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this_cpu_write(mce_next_interval, iv);
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__start_timer(t, iv);
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}
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}
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static void __mcheck_cpu_setup_timer(void)
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