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riscv: dts: allwinner: d1s-t113: add hstimer node

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Describe high speed timer block on Allwinner D1S-T113.

Tested on LCPI-PC-T113/F113:
- hstimer is registered as clocksource
- switching clocksource at runtime works
- after rating increase hstimer operates as a broadcast clockevent device

Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Link: https://patch.msgid.link/20260506-h616-t113s-hstimer-v4-3-591d425863d6@mmpsystems.pl
[wens@kernel.org: change subject prefix from "arm" to "riscv"]
[wens@kernel.org: fix interrupt representation]
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
This commit is contained in:
Michal Piekos 2026-05-06 17:10:28 +02:00 committed by Chen-Yu Tsai
parent 402e845f9d
commit 003ff31226
1 changed files with 9 additions and 0 deletions
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9
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
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@ -295,6 +295,15 @@ timer: timer@2050000 {
clocks = <&dcxo>;
};
hstimer@3008000 {
compatible = "allwinner,sun20i-d1-hstimer";
reg = <0x03008000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(55) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(56) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HSTIMER>;
resets = <&ccu RST_BUS_HSTIMER>;
};
wdt: watchdog@20500a0 {
compatible = "allwinner,sun20i-d1-wdt-reset",
"allwinner,sun20i-d1-wdt";